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74 lines
2.0 KiB
Verilog
74 lines
2.0 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 23-10-2019
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*/
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module jt51_csr_ch(
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input rst,
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input clk,
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input cen,
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input [ 7:0] din,
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input up_rl_ch,
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input up_fb_ch,
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input up_con_ch,
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input up_kc_ch,
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input up_kf_ch,
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input up_ams_ch,
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input up_pms_ch,
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output [1:0] rl,
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output [2:0] fb,
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output [2:0] con,
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output [6:0] kc,
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output [5:0] kf,
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output [1:0] ams,
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output [2:0] pms
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);
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wire [1:0] rl_in = din[7:6];
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wire [2:0] fb_in = din[5:3];
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wire [2:0] con_in = din[2:0];
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wire [6:0] kc_in = din[6:0];
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wire [5:0] kf_in = din[7:2];
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wire [1:0] ams_in = din[1:0];
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wire [2:0] pms_in = din[6:4];
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wire [25:0] reg_in = {
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up_rl_ch ? rl_in : rl,
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up_fb_ch ? fb_in : fb,
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up_con_ch ? con_in : con,
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up_kc_ch ? kc_in : kc,
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up_kf_ch ? kf_in : kf,
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up_ams_ch ? ams_in : ams,
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up_pms_ch ? pms_in : pms };
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wire [25:0] reg_out;
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assign { rl, fb, con, kc, kf, ams, pms } = reg_out;
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jt51_sh #( .width(26), .stages(8)) u_regop(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( reg_in ),
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.drop ( reg_out )
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);
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endmodule |