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20 lines
462 B
VHDL
20 lines
462 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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package jt89 is
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component jt89
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port
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(
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rst : in std_logic;
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clk : in std_logic; -- CPU clock
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clk_en : in std_logic := '1'; -- optional clock enable, if not needed leave as '1'
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din : in std_logic_vector(7 downto 0);
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wr_n : in std_logic;
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ready : out std_logic;
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sound : out std_logic_vector(10 downto 0) -- signed
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);
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end component;
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end;
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