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11 lines
906 B
Plaintext
11 lines
906 B
Plaintext
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) jt89_sms.vhd ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89_sms.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89_noise.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89_vol.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89_mixer.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt89_tone.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mixer/jt12_interpol.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mixer/jt12_comb.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mixer/jt12_dac2.v ]
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