mirror of
https://github.com/Gehstock/Mist_FPGA.git
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137 lines
4.0 KiB
VHDL
137 lines
4.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's SN76489AN.
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--
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-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
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--
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-- Clock Divider Circuit
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity sn76489_clock_div is
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generic (
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clock_div_16_g : integer := 1
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);
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port (
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clock_i : in std_logic;
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clock_en_i : in std_logic;
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res_n_i : in std_logic;
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clk_en_o : out boolean
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);
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end sn76489_clock_div;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of sn76489_clock_div is
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signal cnt_s,
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cnt_q : std_logic_vector(3 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential counter element.
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--
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seq: process (clock_i, res_n_i)
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begin
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if res_n_i = '0' then
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cnt_q <= (others => '0');
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elsif clock_i'event and clock_i = '1' then
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cnt_q <= cnt_s;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process comb
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--
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-- Purpose:
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-- Implements the combinational counter logic.
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--
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comb: process (clock_en_i,
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cnt_q)
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begin
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-- default assignments
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cnt_s <= cnt_q;
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clk_en_o <= false;
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if clock_en_i = '1' then
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if cnt_q = 0 then
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clk_en_o <= true;
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if clock_div_16_g = 1 then
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cnt_s <= conv_std_logic_vector(15, cnt_q'length);
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elsif clock_div_16_g = 0 then
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cnt_s <= conv_std_logic_vector( 1, cnt_q'length);
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else
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-- pragma translate_off
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assert false
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report "Generic clock_div_16_g must be either 0 or 1."
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severity failure;
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-- pragma translate_on
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end if;
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else
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cnt_s <= cnt_q - 1;
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end if;
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end if;
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end process comb;
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--
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-----------------------------------------------------------------------------
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end rtl;
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