mirror of
https://github.com/Gehstock/Mist_FPGA.git
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203 lines
6.1 KiB
VHDL
203 lines
6.1 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's SN76489AN.
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--
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-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
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--
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-- Chip Toplevel
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--
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-- References:
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--
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-- * TI Data sheet SN76489.pdf
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-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
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--
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-- * John Kortink's article on the SN76489:
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-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
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--
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-- * Maxim's "SN76489 notes" in
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-- http://www.smspower.org/maxim/docs/SN76489.txt
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity sn76489_top is
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generic (
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clock_div_16_g : integer := 1
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);
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port (
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clock_i : in std_logic;
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clock_en_i : in std_logic;
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res_n_i : in std_logic;
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ce_n_i : in std_logic;
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we_n_i : in std_logic;
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ready_o : out std_logic;
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d_i : in std_logic_vector(0 to 7);
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aout_o : out std_logic_vector(0 to 7)
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);
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end sn76489_top;
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library ieee;
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use ieee.numeric_std.all;
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architecture struct of sn76489_top is
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signal clk_en_s : boolean;
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signal tone1_we_s,
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tone2_we_s,
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tone3_we_s,
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noise_we_s : boolean;
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signal r2_s : std_logic;
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signal tone1_s,
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tone2_s,
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tone3_s,
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noise_s : std_logic_vector(0 to 7);
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signal tone3_ff_s : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Clock Divider
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-----------------------------------------------------------------------------
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clock_div_b : entity work.sn76489_clock_div
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generic map (
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clock_div_16_g => clock_div_16_g
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)
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port map (
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clock_i => clock_i,
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clock_en_i => clock_en_i,
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res_n_i => res_n_i,
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clk_en_o => clk_en_s
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);
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-----------------------------------------------------------------------------
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-- Latch Control = CPU Interface
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-----------------------------------------------------------------------------
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latch_ctrl_b : entity work.sn76489_latch_ctrl
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port map (
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clock_i => clock_i,
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clk_en_i => clk_en_s,
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res_n_i => res_n_i,
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ce_n_i => ce_n_i,
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we_n_i => we_n_i,
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d_i => d_i,
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ready_o => ready_o,
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tone1_we_o => tone1_we_s,
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tone2_we_o => tone2_we_s,
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tone3_we_o => tone3_we_s,
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noise_we_o => noise_we_s,
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r2_o => r2_s
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);
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-----------------------------------------------------------------------------
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-- Tone Channel 1
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-----------------------------------------------------------------------------
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tone1_b : entity work.sn76489_tone
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port map (
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clock_i => clock_i,
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clk_en_i => clk_en_s,
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res_n_i => res_n_i,
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we_i => tone1_we_s,
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d_i => d_i,
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r2_i => r2_s,
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ff_o => open,
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tone_o => tone1_s
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);
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-----------------------------------------------------------------------------
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-- Tone Channel 2
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-----------------------------------------------------------------------------
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tone2_b : entity work.sn76489_tone
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port map (
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clock_i => clock_i,
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clk_en_i => clk_en_s,
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res_n_i => res_n_i,
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we_i => tone2_we_s,
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d_i => d_i,
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r2_i => r2_s,
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ff_o => open,
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tone_o => tone2_s
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);
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-----------------------------------------------------------------------------
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-- Tone Channel 3
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-----------------------------------------------------------------------------
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tone3_b : entity work.sn76489_tone
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port map (
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clock_i => clock_i,
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clk_en_i => clk_en_s,
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res_n_i => res_n_i,
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we_i => tone3_we_s,
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d_i => d_i,
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r2_i => r2_s,
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ff_o => tone3_ff_s,
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tone_o => tone3_s
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);
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-----------------------------------------------------------------------------
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-- Noise Channel
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-----------------------------------------------------------------------------
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noise_b : entity work.sn76489_noise
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port map (
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clock_i => clock_i,
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clk_en_i => clk_en_s,
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res_n_i => res_n_i,
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we_i => noise_we_s,
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d_i => d_i,
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r2_i => r2_s,
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tone3_ff_i => tone3_ff_s,
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noise_o => noise_s
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);
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aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
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end struct;
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