mirror of
https://github.com/Gehstock/Mist_FPGA.git
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212 lines
7.0 KiB
VHDL
212 lines
7.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- i8244 Video Display Controller
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--
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-- $Id: i8244_grid.vhd,v 1.14 2007/02/05 22:08:59 arnim Exp $
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--
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-- Grid Generator
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2007, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.i8244_pack.pos_t;
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use work.i8244_grid_pack.grid_cfg_t;
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entity i8244_grid is
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port (
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clk_i : in std_logic;
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clk_en_i : in boolean;
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res_i : in boolean;
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hpos_i : in pos_t;
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vpos_i : in pos_t;
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hbl_i : in std_logic;
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vbl_i : in std_logic;
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grid_cfg_i : in grid_cfg_t;
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grid_hpix_o : out std_logic;
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grid_vpix_o : out std_logic;
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grid_dpix_o : out std_logic
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);
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end i8244_grid;
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library ieee;
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use ieee.numeric_std.all;
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use work.i8244_pack.all;
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use work.i8244_grid_pack.all;
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architecture rtl of i8244_grid is
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-----------------------------------------------------------------------------
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-- Grid geometry:
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--
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-- number of horizontal grid segments
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constant grid_hnum_c : natural := 10;
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-- left horizontal offset (3.54 MHz clocks)
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constant grid_hoffset_c : natural := 16#08#;
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-- horizontal width of vertical segments and dots (3.54 MHz clock)
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constant grid_hwidth_c : natural := 16#02#;
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-- length/spacing of horizontal grid segments (3.54 MHz clock)
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constant grid_hspace_c : natural := 16#10#;
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--
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-- number of vertical grid segments
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constant grid_vnum_c : natural := 9;
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-- upper vertical offset (scanlines)
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constant grid_voffset_c : natural := 16#18#;
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-- vertical height of horizontal segments and dots (scanlines)
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constant grid_vwidth_c : natural := 16#03#;
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-- height/spacing of vertical grid segments (scanlines)
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constant grid_vspace_c : natural := 16#18#;
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--
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-----------------------------------------------------------------------------
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signal hgrid_q,
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vgrid_q,
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dgrid_q : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Process grid_gen
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--
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-- Purpose:
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-- Generates the grid activity signals for horizontal and vertical
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-- grid elements.
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--
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grid_gen: process (clk_i, res_i)
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variable hpos_v,
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vpos_v : natural;
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variable upper_v,
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lower_v,
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left_v,
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right_v,
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dot_v : natural;
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begin
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if res_i then
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hgrid_q <= '0';
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vgrid_q <= '0';
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dgrid_q <= '0';
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elsif rising_edge(clk_i) then
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-- horizontal positioning bases on 3.54 MHz pixels/clocks
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hpos_v := to_integer(hpos_i(pos_t'high downto 1));
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-- vertical positioning bases on scanlines (no scaling etc.)
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vpos_v := to_integer(vpos_i);
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if clk_en_i then
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hgrid_q <= '0';
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dgrid_q <= '0';
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vgrid_q <= '0';
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-- horizontal bars ----------------------------------------------------
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for hbar in 0 to grid_vnum_c-1 loop
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upper_v := grid_voffset_c + hbar * grid_vspace_c;
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lower_v := upper_v + grid_vwidth_c;
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-- check upper and lower bar/dot limits
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if vpos_v >= upper_v and vpos_v < lower_v then
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for idx in 0 to grid_hnum_c-2 loop
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left_v := grid_hoffset_c + idx * grid_hspace_c;
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right_v := left_v + grid_hspace_c + grid_hwidth_c;
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dot_v := left_v + grid_hwidth_c;
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-- check left limit
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if hpos_v >= left_v then
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-- bar: check right limit
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if hpos_v < right_v then
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if grid_cfg_i.bars.hbars(hbar)(idx) = '1' then
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hgrid_q <= '1';
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end if;
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end if;
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-- dot: check right limit
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if hpos_v < dot_v then
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dgrid_q <= '1';
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end if;
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end if;
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end loop;
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end if;
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end loop;
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-- vertical bars ------------------------------------------------------
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for vbar in 0 to grid_hnum_c-1 loop
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left_v := grid_hoffset_c + vbar * grid_hspace_c;
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if grid_cfg_i.wide = '1' then
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-- wide grid extends over horizontal space
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right_v := left_v + grid_hspace_c;
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else
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-- normal grid
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right_v := left_v + grid_hwidth_c;
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end if;
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-- check left and right bar limits
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if hpos_v >= left_v and hpos_v < right_v then
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for idx in 0 to grid_vnum_c-2 loop
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upper_v := grid_voffset_c + idx * grid_vspace_c;
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lower_v := upper_v + grid_vspace_c;
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-- check upper and lower bar limits
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if vpos_v >= upper_v and vpos_v < lower_v then
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if grid_cfg_i.bars.vbars(vbar)(idx) = '1' then
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vgrid_q <= '1';
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end if;
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end if;
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end loop;
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end if;
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end loop;
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end if;
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end if;
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end process grid_gen;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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grid_hpix_o <= hgrid_q;
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grid_vpix_o <= vgrid_q;
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grid_dpix_o <= dgrid_q;
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end rtl;
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