mirror of
https://github.com/Gehstock/Mist_FPGA.git
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244 lines
7.3 KiB
VHDL
244 lines
7.3 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_hor_vert.vhd,v 1.11 2006/06/18 10:47:01 arnim Exp $
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--
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-- Horizontal / Vertical Timing Generator
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.vdp18_pack.opmode_t;
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use work.vdp18_pack.hv_t;
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entity vdp18_hor_vert is
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port (
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clock_i : in std_logic;
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clk_en_5m37_i : in boolean;
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reset_i : in boolean;
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opmode_i : in opmode_t;
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ntsc_pal_i : in std_logic;
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num_pix_o : out hv_t;
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num_line_o : out hv_t;
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vert_inc_o : out boolean;
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hsync_n_o : out std_logic;
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vsync_n_o : out std_logic;
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blank_o : out boolean;
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cnt_hor_o : out std_logic_vector(8 downto 0);
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cnt_ver_o : out std_logic_vector(7 downto 0)
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);
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end vdp18_hor_vert;
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use work.vdp18_pack.all;
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architecture rtl of vdp18_hor_vert is
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signal last_line_s : hv_t;
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signal first_line_s : hv_t;
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signal first_pix_s : hv_t;
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signal last_pix_s : hv_t;
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signal cnt_hor_q : hv_t;
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signal cnt_vert_q : hv_t;
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signal vert_inc_s : boolean;
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signal hblank_q,
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vblank_q : boolean;
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signal cnt_hor_s : unsigned(8 downto 0);
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signal cnt_ver_s : unsigned(7 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Prepare comparison signals for NTSC and PAL.
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--
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first_line_s <= hv_first_line_ntsc_c when ntsc_pal_i = '0' else hv_first_line_pal_c;
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last_line_s <= hv_last_line_ntsc_c when ntsc_pal_i = '0' else hv_last_line_pal_c;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process opmode_mux
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--
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-- Purpose:
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-- Generates the horizontal counter limits based on the current operating
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-- mode.
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--
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opmode_mux: process (opmode_i)
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begin
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if opmode_i = OPMODE_TEXTM then
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first_pix_s <= hv_first_pix_text_c;
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last_pix_s <= hv_last_pix_text_c;
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else
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first_pix_s <= hv_first_pix_graph_c;
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last_pix_s <= hv_last_pix_graph_c;
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end if;
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end process opmode_mux;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process counters
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--
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-- Purpose:
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-- Implements the horizontal and vertical counters.
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--
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counters: process (clock_i, reset_i, first_line_s)
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begin
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if reset_i then
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cnt_hor_q <= hv_first_pix_text_c;
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cnt_vert_q <= first_line_s;
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hsync_n_o <= '1';
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vsync_n_o <= '1';
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hblank_q <= false;
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vblank_q <= false;
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elsif clock_i'event and clock_i = '1' then
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if clk_en_5m37_i then
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-- The horizontal counter ---------------------------------------------
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if cnt_hor_q = last_pix_s then
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cnt_hor_q <= first_pix_s;
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else
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cnt_hor_q <= cnt_hor_q + 1;
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end if;
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-- The vertical counter -----------------------------------------------
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if cnt_vert_q = last_line_s then
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cnt_vert_q <= first_line_s;
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elsif vert_inc_s then
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-- increment when horizontal counter is at trigger position
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cnt_vert_q <= cnt_vert_q + 1;
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end if;
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-- Horizontal sync ----------------------------------------------------
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if cnt_hor_q = -64 then -- -64 -44 -56
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hsync_n_o <= '0';
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elsif cnt_hor_q = -38 then -- -38 -18 -30
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hsync_n_o <= '1';
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end if;
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if cnt_hor_q = -72 then -- -72 -62 -69
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hblank_q <= true;
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elsif cnt_hor_q = -13 then -- -14 -4 -11
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hblank_q <= false;
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end if;
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-- Vertical sync ------------------------------------------------------
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if ntsc_pal_i = '1' then
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if cnt_vert_q = 244 then
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vsync_n_o <= '0';
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elsif cnt_vert_q = 247 then
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vsync_n_o <= '1';
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end if;
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if cnt_vert_q = 242 then
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vblank_q <= true;
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elsif cnt_vert_q = first_line_s + 13 then
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vblank_q <= false;
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end if;
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else
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if cnt_vert_q = 218 then
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vsync_n_o <= '0';
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elsif cnt_vert_q = 221 then
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vsync_n_o <= '1';
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end if;
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if cnt_vert_q = 215 then
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vblank_q <= true;
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elsif cnt_vert_q = first_line_s + 13 then
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vblank_q <= false;
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end if;
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end if;
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end if;
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end if;
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end process counters;
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--
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-----------------------------------------------------------------------------
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-- comparator for vertical line increment
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vert_inc_s <= clk_en_5m37_i and cnt_hor_q = hv_vertical_inc_c;
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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num_pix_o <= cnt_hor_q;
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num_line_o <= cnt_vert_q;
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vert_inc_o <= vert_inc_s;
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blank_o <= hblank_q or vblank_q;
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-- Generate horizontal and vertical counters for VGA/HDMI (in top)
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process (reset_i, clock_i)
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begin
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if reset_i then
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cnt_hor_s <= (others => '0');
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cnt_ver_s <= (others => '0');
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elsif rising_edge(clock_i) then
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if clk_en_5m37_i then
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if cnt_hor_q = -12 then
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cnt_hor_s <= (others => '0');
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else
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cnt_hor_s <= cnt_hor_s + 1;
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end if;
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if vert_inc_s then
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if cnt_vert_q = -12 then
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cnt_ver_s <= (others => '0');
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else
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cnt_ver_s <= cnt_ver_s + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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cnt_hor_o <= std_logic_vector(cnt_hor_s);
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cnt_ver_o <= std_logic_vector(cnt_ver_s);
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end rtl;
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