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108 lines
2.5 KiB
Verilog
108 lines
2.5 KiB
Verilog
//
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// cdda_fifo.v
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//
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// CDDA FIFO for the MiST board
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// https://github.com/mist-devel
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//
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// Copyright (c) 2022 Gyorgy Szombathelyi
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module cdda_fifo
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(
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input clk_sys,
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input clk_en, // set to 1 when using the stock data_io
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input cen_44100, // 44100 HZ clock enable
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input reset,
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// data_io interface
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output hdd_cdda_req,
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input hdd_cdda_wr,
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input [15:0] hdd_data_out,
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// sample output
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output reg [15:0] cdda_l,
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output reg [15:0] cdda_r
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);
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// 4k x 16bit default FIFO size
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parameter FIFO_DEPTH = 12;
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reg [15:0] fifo[2**FIFO_DEPTH];
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reg [FIFO_DEPTH-1:0] inptr;
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reg [FIFO_DEPTH-1:0] outptr;
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reg [15:0] fifo_out;
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wire [FIFO_DEPTH:0] fifo_used = inptr >= outptr ?
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inptr - outptr :
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inptr - outptr + (2'd2**FIFO_DEPTH);
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assign hdd_cdda_req = fifo_used < ((2'd2**FIFO_DEPTH) - 16'd2352);
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always @(posedge clk_sys) begin
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if (reset)
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inptr <= 0;
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else if (clk_en && hdd_cdda_wr) begin
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fifo[inptr] <= {hdd_data_out[7:0], hdd_data_out[15:8]};
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inptr <= inptr + 1'd1;
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end
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end
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always @(posedge clk_sys) fifo_out <= fifo[outptr];
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reg left = 0;
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reg mute = 1;
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reg fifo_active = 0;
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always @(posedge clk_sys) begin
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if (reset) begin
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outptr <= 0;
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fifo_active <= 0;
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mute <= 1;
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left <= 0;
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cdda_l <= 0;
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cdda_r <= 0;
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end else begin
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if (cen_44100) begin
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if (fifo_used >= 2352)
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fifo_active <= 1;
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if (outptr + 2'd2 == inptr)
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fifo_active <= 0;
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if (fifo_active) begin
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outptr <= outptr + 1'd1;
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left <= 1;
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mute <= 0;
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end else
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mute <= 1;
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end
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if (left) begin
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outptr <= outptr + 1'd1;
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left <= 0;
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end
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if (mute) begin
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cdda_l <= 0;
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cdda_r <= 0;
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end else begin
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if (left)
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cdda_l <= fifo_out;
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else
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cdda_r <= fifo_out;
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end
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end
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end
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endmodule
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