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32 lines
681 B
VHDL
32 lines
681 B
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE WORK.GAME_TYPES.ALL;
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ENTITY GAME_RANDOMGEN IS
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PORT
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(
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-- INPUT
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clk : IN STD_LOGIC;
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-- OUTPUT
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random_num : OUT STD_LOGIC_VECTOR(3 downto 0)
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);
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END GAME_RANDOMGEN;
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ARCHITECTURE behavior of GAME_RANDOMGEN IS
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BEGIN
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PROCESS(clk)
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variable rand_temp : std_logic_vector(GRID_WIDTH-1 downto 0):=("1000");
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variable temp : std_logic := '0';
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BEGIN
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if(rising_edge(clk)) then
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temp := rand_temp(GRID_WIDTH-1) xor rand_temp(GRID_WIDTH-2);
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rand_temp(GRID_WIDTH-1 downto 1) := rand_temp(GRID_WIDTH-2 downto 0);
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rand_temp(0) := temp;
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end if;
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random_num <= rand_temp;
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END PROCESS;
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END behavior; |