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21 lines
381 B
Systemverilog
21 lines
381 B
Systemverilog
module cart(
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input clk0,
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input [15:0] addr,
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input [7:0] data_i,
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output [7:0] data_o,
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output reg nmi,
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input reset,
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input romL, // romL signal in
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input romH,
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input rw_pla_n,
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input ba,
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input cia_pla_n,
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input cia_n,
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input cnt,
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input exram_n,
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input sp,
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input rw_n,
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input irq_n
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);
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endmodule
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