mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-05-04 23:35:48 +00:00
360 lines
11 KiB
Systemverilog
360 lines
11 KiB
Systemverilog
//
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// gb.v
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//
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// Gameboy for the MIST board https://github.com/mist-devel
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module gb (
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input reset,
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input clk,
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input fast_boot,
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input [7:0] joystick,
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// cartridge interface
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// can adress up to 1MB ROM
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output [15:0] cart_addr,
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output cart_rd,
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output cart_wr,
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input [7:0] cart_do,
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output [7:0] cart_di,
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// audio
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output [15:0] audio_l,
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output [15:0] audio_r,
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// lcd interface
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output lcd_clkena,
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output [1:0] lcd_data,
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output [1:0] lcd_mode,
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output lcd_on
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);
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// include cpu
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wire [15:0] cpu_addr;
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wire [7:0] cpu_do;
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wire sel_timer = (cpu_addr[15:4] == 12'hff0) && (cpu_addr[3:2] == 2'b01);
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wire sel_video_reg = cpu_addr[15:4] == 12'hff4;
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wire sel_video_oam = cpu_addr[15:8] == 8'hfe;
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wire sel_joy = cpu_addr == 16'hff00; // joystick controller
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wire sel_rom = !cpu_addr[15]; // lower 32k are rom
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wire sel_cram = cpu_addr[15:13] == 3'b101; // 8k cart ram at $a000
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wire sel_vram = cpu_addr[15:13] == 3'b100; // 8k video ram at $8000
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wire sel_ie = cpu_addr == 16'hffff; // interupt enable
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wire sel_if = cpu_addr == 16'hff0f; // interupt flag
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wire sel_iram = (cpu_addr[15:14] == 2'b11) && (cpu_addr[15:8] != 8'hff); // 8k internal ram at $c000
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wire sel_zpram = (cpu_addr[15:7] == 9'b111111111) && // 127 bytes zero pageram at $ff80
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(cpu_addr != 16'hffff);
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wire sel_audio = (cpu_addr[15:8] == 8'hff) && // audio reg ff10 - ff3f
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((cpu_addr[7:5] == 3'b001) || (cpu_addr[7:4] == 4'b0001));
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// the boot roms sees a special $42 flag in $ff50 if it's supposed to to a fast boot
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wire sel_fast = fast_boot && cpu_addr == 16'hff50 && boot_rom_enabled;
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// http://gameboy.mongenel.com/dmg/asmmemmap.html
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wire [7:0] cpu_di =
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irq_ack?irq_vec:
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sel_fast?8'h42: // fast boot flag
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sel_joy?joy_do: // joystick register
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sel_timer?timer_do: // timer registers
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sel_video_reg?video_do: // video registers
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sel_video_oam?video_do: // video object attribute memory
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sel_audio?audio_do: // audio registers
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sel_rom?rom_do: // boot rom + cartridge rom
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sel_cram?rom_do: // cartridge ram
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sel_vram?vram_do: // vram
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sel_zpram?zpram_do: // zero page ram
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sel_iram?iram_do: // internal ram
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sel_ie?{3'b000, ie_r}: // interrupt enable register
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sel_if?{3'b000, if_r}: // interrupt flag register
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8'hff;
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wire cpu_wr_n;
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wire cpu_rd_n;
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wire cpu_iorq_n;
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wire cpu_m1_n;
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wire cpu_mreq_n;
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GBse cpu (
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.RESET_n ( !reset ),
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.CLK_n ( clk ),
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.CLKEN ( 1'b1 ),
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.WAIT_n ( 1'b1 ),
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.INT_n ( irq_n ),
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.NMI_n ( 1'b1 ),
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.BUSRQ_n ( 1'b1 ),
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.M1_n ( cpu_m1_n ),
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.MREQ_n ( cpu_mreq_n ),
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.IORQ_n ( cpu_iorq_n ),
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.RD_n ( cpu_rd_n ),
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.WR_n ( cpu_wr_n ),
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.RFSH_n ( ),
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.HALT_n ( ),
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.BUSAK_n ( ),
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.A ( cpu_addr ),
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.DI ( cpu_di ),
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.DO ( cpu_do )
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);
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// --------------------------------------------------------------------
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// ------------------------------ audio -------------------------------
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// --------------------------------------------------------------------
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wire audio_rd = !cpu_rd_n && sel_audio;
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wire audio_wr = !cpu_wr_n && sel_audio;
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wire [7:0] audio_do;
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gbc_snd audio (
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.clk ( clk ),
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.reset ( reset ),
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.s1_read ( audio_rd ),
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.s1_write ( audio_wr ),
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.s1_addr ( cpu_addr[5:0] ),
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.s1_readdata ( audio_do ),
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.s1_writedata ( cpu_do ),
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.snd_left ( audio_l ),
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.snd_right ( audio_r )
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);
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// --------------------------------------------------------------------
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// ------------------------------ inputs ------------------------------
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// --------------------------------------------------------------------
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wire [3:0] joy_p4 = { !joystick[2], !joystick[3], !joystick[1], !joystick[0] };
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wire [3:0] joy_p5 = { !joystick[7], !joystick[6], !joystick[5], !joystick[4] };
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reg [1:0] p54;
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always @(posedge clk) begin
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if(reset)
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p54 <= 2'b11;
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else if(sel_joy && !cpu_wr_n)
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p54 <= cpu_do[5:4];
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end
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wire [7:0] joy_do = { 2'b11, p54,
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((!p54[0])?joy_p4:4'hf) & ((!p54[1])?joy_p5:4'hf) };
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// --------------------------------------------------------------------
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// ---------------------------- interrupts ----------------------------
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// --------------------------------------------------------------------
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// interrupt flags are set when the event happens or when the cpu writes
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// the register to 1. The "highest" one active is cleared when the cpu
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// runs an interrupt ack cycle or when it writes a 0 to the register
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wire irq_ack = !cpu_iorq_n && !cpu_m1_n;
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// latch irq vector at the begin of the irq ack
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reg [7:0] irq_vec;
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always @(posedge irq_ack)
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irq_vec <=
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if_r[0]?8'h40: // vsync
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if_r[1]?8'h48: // lcdc
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if_r[2]?8'h50: // timer
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if_r[3]?8'h58: // serial
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if_r[4]?8'h60: // input
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8'h55;
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wire vs = (lcd_mode == 2'b01);
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reg vsD, vsD2;
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reg [3:0] inputD, inputD2;
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// irq is low when an enable irq is active
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wire irq_n = !(ie_r & if_r);
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reg [4:0] if_r;
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reg [4:0] ie_r; // writing $ffff sets the irq enable mask
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always @(posedge clk) begin
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if(reset) begin
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ie_r <= 5'h00;
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if_r <= 5'h00;
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end
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// rising edge on vs
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vsD <= vs;
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vsD2 <= vsD;
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if(vsD && !vsD2) if_r[0] <= 1'b1;
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// video irq already is a 1 clock event
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if(video_irq) if_r[1] <= 1'b1;
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// timer_irq already is a 1 clock event
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if(timer_irq) if_r[2] <= 1'b1;
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// falling edge on any input line P10..P13
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inputD <= joy_p4 | joy_p5;
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inputD2 <= inputD;
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if(~inputD & inputD2) if_r[4] <= 1'b1;
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// cpu acknowledges irq. this clears the active irq with hte
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// highest priority
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if(irq_ack) begin
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if(if_r[0] && ie_r[0]) if_r[0] <= 1'b0;
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else if(if_r[1] && ie_r[1]) if_r[1] <= 1'b0;
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else if(if_r[2] && ie_r[2]) if_r[2] <= 1'b0;
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else if(if_r[3] && ie_r[3]) if_r[3] <= 1'b0;
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else if(if_r[4] && ie_r[4]) if_r[4] <= 1'b0;
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end
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// cpu writes interrupt enable register
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if(sel_ie && !cpu_wr_n)
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ie_r <= cpu_do[4:0];
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// cpu writes interrupt flag register
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if(sel_if && !cpu_wr_n)
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if_r <= cpu_do[4:0];
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end
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// --------------------------------------------------------------------
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// ------------------------------ timer -------------------------------
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// --------------------------------------------------------------------
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wire timer_irq;
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wire [7:0] timer_do;
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timer timer (
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.reset ( reset ),
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.clk ( clk ),
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.irq ( timer_irq ),
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.cpu_sel ( sel_timer ),
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.cpu_addr ( cpu_addr[1:0] ),
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.cpu_wr ( !cpu_wr_n ),
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.cpu_di ( cpu_do ),
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.cpu_do ( timer_do )
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);
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// --------------------------------------------------------------------
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// ------------------------------ video -------------------------------
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// --------------------------------------------------------------------
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// cpu tries to read or write the lcd controller registers
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wire video_irq;
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wire [7:0] video_do;
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wire [12:0] video_addr;
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wire [15:0] dma_addr;
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wire video_rd, dma_rd;
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wire [7:0] dma_data = (dma_addr[15:14]==2'b11)?iram_do:cart_do;
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video video (
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.reset ( reset ),
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.clk ( clk ),
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.irq ( video_irq ),
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.cpu_sel_reg ( sel_video_reg ),
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.cpu_sel_oam ( sel_video_oam ),
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.cpu_addr ( cpu_addr[7:0] ),
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.cpu_wr ( !cpu_wr_n ),
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.cpu_di ( cpu_do ),
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.cpu_do ( video_do ),
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.lcd_on ( lcd_on ),
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.lcd_clkena ( lcd_clkena ),
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.lcd_data ( lcd_data ),
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.mode ( lcd_mode ),
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.vram_rd ( video_rd ),
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.vram_addr ( video_addr ),
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.vram_data ( vram_do ),
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.dma_rd ( dma_rd ),
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.dma_addr ( dma_addr ),
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.dma_data ( dma_data )
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);
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// total 8k vram from $8000 to $9fff
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wire cpu_wr_vram = sel_vram && !cpu_wr_n;
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wire [7:0] vram_do;
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wire vram_wren = video_rd?1'b0:cpu_wr_vram;
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wire [12:0] vram_addr = video_rd?video_addr:cpu_addr[12:0];
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vram vram (
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.clock ( clk ),
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.address ( vram_addr ),
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.wren ( vram_wren ),
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.data ( cpu_do ),
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.q ( vram_do )
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);
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// --------------------------------------------------------------------
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// -------------------------- zero page ram ---------------------------
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// --------------------------------------------------------------------
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// 127 bytes internal zero page ram from $ff80 to $fffe
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wire cpu_wr_zpram = sel_zpram && !cpu_wr_n;
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wire [7:0] zpram_do;
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zpram zpram (
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.clock ( clk ),
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.address ( cpu_addr[6:0] ),
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.wren ( cpu_wr_zpram ),
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.data ( cpu_do ),
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.q ( zpram_do )
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);
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// --------------------------------------------------------------------
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// ------------------------- 8k internal ram --------------------------
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// --------------------------------------------------------------------
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wire iram_wren = dma_rd?1'b0:cpu_wr_iram;
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wire [12:0] iram_addr = dma_rd?dma_addr[12:0]:cpu_addr[12:0];
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wire cpu_wr_iram = sel_iram && !cpu_wr_n;
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wire [7:0] iram_do;
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iram iram (
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.clock ( clk ),
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.address ( iram_addr[12:0]),
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.wren ( iram_wren ),
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.data ( cpu_do ),
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.q ( iram_do )
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);
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// --------------------------------------------------------------------
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// ------------------------ internal boot rom -------------------------
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// --------------------------------------------------------------------
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// writing 01 to $ff50 disables the internal rom
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reg boot_rom_enabled;
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always @(posedge clk) begin
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if(reset)
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boot_rom_enabled <= 1'b1;
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else if((cpu_addr == 16'hff50) && !cpu_wr_n && cpu_do[0])
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boot_rom_enabled <= 1'b0;
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end
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// combine boot rom data with cartridge data
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wire [7:0] rom_do = ((cpu_addr[14:8] == 7'h00) && boot_rom_enabled)?boot_rom_do:cart_do;
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assign cart_di = cpu_do;
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assign cart_addr = dma_rd?dma_addr:cpu_addr;
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assign cart_rd = dma_rd || ((sel_rom || sel_cram) && !cpu_rd_n);
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assign cart_wr = (sel_rom || sel_cram) && !cpu_wr_n;
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wire [7:0] boot_rom_do;
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BROM BROM (
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.addr ( cpu_addr[7:0] ),
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.clk ( clk ),
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.data ( boot_rom_do )
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);
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endmodule
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