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57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
/* ===============================================================
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(C) 2002 Bird Computer
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All rights reserved.
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addsub.v
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Please read the Licensing Agreement (license.html file).
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Use of this file is subject to the license agreement.
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You are free to use and modify this code for non-commercial
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or evaluation purposes.
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If you do modify the code, please state the origin and
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note that you have modified the code.
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Adder / subtractor module with carry in, carry and overflow
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outputs. Parameterized width with a default of 32 bits.
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Note: we use a trick in the adder to get carry generated
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and an adder / subtractor packed into 1 LUT per bit. The
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'a' and 'b' inputs are specified with an extra unused bit
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on the left (pass a zero for this bit).
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Also note that the carry (borrow) input for a subtract has
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to be inverted. IE. ci = 1 = no borrow in.
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=============================================================== */
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`timescale 1ps / 1ps
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module addsub(op, ci, a, b, o, co, v);
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parameter DBW = 32;
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input op; // 0 = add, 1 = sub
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input ci; // carry in
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input [DBW:0] a, b; // operands input
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output [DBW-1:0] o; // result
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output co; // carry out
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output v; // overflow
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reg [DBW+1:0] sum;
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// Note XST does not like assignments to bit group on LHS
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// for subtract
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always @(op or ci or a or b) begin
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case(op)
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1'd0: sum = {a,ci} + {b,1'b1};
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1'd1: sum = {a,ci} - {b,1'b1};
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endcase
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end
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assign o = sum[DBW:1];
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assign co = sum[DBW+1];
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// compute overflow
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assign v = (op ^ o[DBW-1] ^ b[DBW-1]) & (~op ^ a[DBW-1] ^ b[DBW-1]);
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endmodule
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