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41 lines
1.3 KiB
Verilog
41 lines
1.3 KiB
Verilog
/*============================================================================
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74LS42 - BCD to decimal decoder
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Copyright (C) 2022 - Jim Gregory - https://github.com/JimmyStones/
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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`timescale 1 ps / 1 ps
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`default_nettype none
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module ls42
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(
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input wire a, b, c, d,
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output wire [9:0] o
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);
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assign o[0] = ~(~a && ~b && ~c && ~d);
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assign o[1] = ~(a && ~b && ~c && ~d);
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assign o[2] = ~(~a && b && ~c && ~d);
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assign o[3] = ~(a && b && ~c && ~d);
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assign o[4] = ~(~a && ~b && c && ~d);
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assign o[5] = ~(a && ~b && c && ~d);
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assign o[6] = ~(~a && b && c && ~d);
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assign o[7] = ~(a && b && c && ~d);
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assign o[8] = ~(~a && ~b && ~c && d);
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assign o[9] = ~(a && ~b && ~c && d);
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endmodule
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