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https://github.com/Gehstock/Mist_FPGA.git
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153 lines
5.0 KiB
VHDL
153 lines
5.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- FPGA Colecovision
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--
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-- $Id: cv_ctrl.vhd,v 1.3 2006/01/08 23:58:04 arnim Exp $
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--
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-- Controller Interface Module
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity cv_ctrl is
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port (
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clock_i : in std_logic;
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clk_en_3m58_i : in std_logic;
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reset_n_i : in std_logic;
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ctrl_en_key_n_i : in std_logic;
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ctrl_en_joy_n_i : in std_logic;
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a1_i : in std_logic;
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ctrl_p1_i : in std_logic_vector(2 downto 1);
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ctrl_p2_i : in std_logic_vector(2 downto 1);
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ctrl_p3_i : in std_logic_vector(2 downto 1);
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ctrl_p4_i : in std_logic_vector(2 downto 1);
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ctrl_p5_o : out std_logic_vector(2 downto 1);
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ctrl_p6_i : in std_logic_vector(2 downto 1);
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ctrl_p7_i : in std_logic_vector(2 downto 1);
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ctrl_p8_o : out std_logic_vector(2 downto 1);
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ctrl_p9_i : in std_logic_vector(2 downto 1);
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d_o : out std_logic_vector(7 downto 0)
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);
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end cv_ctrl;
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architecture rtl of cv_ctrl is
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signal sel_q : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the R/S flip-flop which selects the controller function.
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--
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seq: process (clock_i, reset_n_i)
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variable ctrl_en_v : std_logic_vector(1 downto 0);
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begin
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if reset_n_i = '0' then
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sel_q <= '0';
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elsif clock_i'event and clock_i = '1' then
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if clk_en_3m58_i = '1' then
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ctrl_en_v := ctrl_en_key_n_i & ctrl_en_joy_n_i;
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case ctrl_en_v is
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when "01" =>
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sel_q <= '0';
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when "10" =>
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sel_q <= '1';
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when others =>
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null;
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end case;
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end if;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Controller select
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-----------------------------------------------------------------------------
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ctrl_p5_o(1) <= sel_q;
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ctrl_p5_o(2) <= sel_q;
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ctrl_p8_o(1) <= not sel_q;
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ctrl_p8_o(2) <= not sel_q;
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-----------------------------------------------------------------------------
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-- Process ctrl_read
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--
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-- Purpose:
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-- Read multiplexer for the controller lines.
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-- NOTE: The quadrature decoders are not implemented!
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--
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ctrl_read: process (a1_i,
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ctrl_p1_i, ctrl_p2_i, ctrl_p3_i, ctrl_p4_i,
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ctrl_p6_i, ctrl_p7_i)
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variable idx_v : natural range 1 to 2;
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begin
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if a1_i = '0' then
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-- read controller #1
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idx_v := 1;
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else
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-- read controller #2
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idx_v := 2;
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end if;
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d_o <= '0' & -- quadrature information
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ctrl_p6_i(idx_v) &
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ctrl_p7_i(idx_v) &
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'1' & -- quadrature information
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ctrl_p3_i(idx_v) &
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ctrl_p2_i(idx_v) &
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ctrl_p4_i(idx_v) &
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ctrl_p1_i(idx_v);
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end process ctrl_read;
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--
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-----------------------------------------------------------------------------
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end rtl;
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