mirror of
https://github.com/Gehstock/Mist_FPGA.git
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143 lines
4.1 KiB
Systemverilog
143 lines
4.1 KiB
Systemverilog
//============================================================================
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//
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// SD card ROM loader and ROM selector for MISTer.
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// Copyright (C) 2019, 2020 Kitrinx (aka Rysha)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS IN THE SOFTWARE.
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//
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//============================================================================
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// ROM layout for Tutankham (index 0 - main CPU board):
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// 0x0000 - 0x0FFF = rom_m1 (m1.1h)
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// 0x1000 - 0x1FFF = rom_m2 (m2.2h)
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// 0x2000 - 0x2FFF = rom_m3 (3j.3h)
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// 0x3000 - 0x3FFF = rom_m4 (m4.4h)
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// 0x4000 - 0x4FFF = rom_m5 (m5.5h)
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// 0x5000 - 0x5FFF = rom_m6 (j6.6h)
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// 0x6000 - 0x6FFF = bank0 (c1.1i)
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// 0x7000 - 0x7FFF = bank1 (c2.2i)
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// 0x8000 - 0x8FFF = bank2 (c3.3i)
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// 0x9000 - 0x9FFF = bank3 (c4.4i)
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// 0xA000 - 0xAFFF = bank4 (c5.5i)
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// 0xB000 - 0xBFFF = bank5 (c6.6i)
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// 0xC000 - 0xCFFF = bank6 (c7.7i)
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// 0xD000 - 0xDFFF = bank7 (c8.8i)
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// 0xE000 - 0xEFFF = bank8 (c9.9i)
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// Sound board ROMs loaded separately via index 1
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module selector
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(
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input logic [24:0] ioctl_addr,
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output logic rom_m1_cs, rom_m2_cs, rom_m3_cs, rom_m4_cs, rom_m5_cs, rom_m6_cs,
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output logic bank0_cs, bank1_cs, bank2_cs, bank3_cs, bank4_cs,
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bank5_cs, bank6_cs, bank7_cs, bank8_cs
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);
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always_comb begin
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{rom_m1_cs, rom_m2_cs, rom_m3_cs, rom_m4_cs, rom_m5_cs, rom_m6_cs,
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bank0_cs, bank1_cs, bank2_cs, bank3_cs, bank4_cs, bank5_cs,
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bank6_cs, bank7_cs, bank8_cs} = 0;
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if(ioctl_addr < 'h1000)
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rom_m1_cs = 1;
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else if(ioctl_addr < 'h2000)
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rom_m2_cs = 1;
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else if(ioctl_addr < 'h3000)
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rom_m3_cs = 1;
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else if(ioctl_addr < 'h4000)
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rom_m4_cs = 1;
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else if(ioctl_addr < 'h5000)
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rom_m5_cs = 1;
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else if(ioctl_addr < 'h6000)
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rom_m6_cs = 1;
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else if(ioctl_addr < 'h7000)
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bank0_cs = 1;
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else if(ioctl_addr < 'h8000)
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bank1_cs = 1;
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else if(ioctl_addr < 'h9000)
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bank2_cs = 1;
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else if(ioctl_addr < 'hA000)
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bank3_cs = 1;
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else if(ioctl_addr < 'hB000)
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bank4_cs = 1;
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else if(ioctl_addr < 'hC000)
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bank5_cs = 1;
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else if(ioctl_addr < 'hD000)
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bank6_cs = 1;
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else if(ioctl_addr < 'hE000)
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bank7_cs = 1;
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else if(ioctl_addr < 'hF000)
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bank8_cs = 1;
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end
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endmodule
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////////////
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// EPROMS //
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////////////
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//Generic 4KB ROM module (12-bit address)
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module eprom_4k
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [11:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(12)) rom
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(
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.clock_a(CLK),
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.address_a(ADDR[11:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[11:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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//Sound board ROM (8KB, 13-bit address) - used by sound board index 1
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module eprom_7
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [12:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(13)) eprom_7
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(
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.clock_a(CLK),
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.address_a(ADDR[12:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[12:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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