mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-26 04:17:10 +00:00
108 lines
2.3 KiB
Systemverilog
108 lines
2.3 KiB
Systemverilog
module orao_mist
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(
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output LED,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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input SPI_SCK,
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output SPI_DO,
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input SPI_DI,
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input SPI_SS2,
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input SPI_SS3,
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input CONF_DATA0,
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input UART_RX,
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output UART_TX,
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input CLOCK_27
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);
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`include "rtl\build_id.v"
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localparam CONF_STR = {
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"Orao;;",
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"T6,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire vid15khz;
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wire ypbpr;
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wire ps2_kbd_clk, ps2_kbd_data;
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wire hs, vs, cs;
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wire video;
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wire [7:0] kbjoy;
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wire clk_50, clk_25, clk_12p5;
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pll pll (
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.inclk0 ( CLOCK_27 ),
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.c0 ( clk_50 ),
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.c1 ( clk_25 ),
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.c2 ( clk_12p5 )
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);
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orao #(.ram_kb(24), .clk_mhz(25), .serial_baud(9600)) orao (
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.n_reset (~(status[0]|status[6]|buttons[1])),
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.clk ( clk_25 ),
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.clkvid ( clk_50 ),//Check
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.video ( video ),
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.hs ( hs ),
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.vs ( vs ),
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.cs ( ),
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.rxd ( UART_RX ),
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.txd ( UART_TX ),
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.rts ( ),
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.key_b ( ),
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.key_c ( ),
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.key_enter ( ),
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.ps2clk ( ps2_kbd_clk ),
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.ps2data ( ps2_kbd_data )
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);
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video_mixer #(.LINE_LENGTH(256), .HALF_DEPTH(1)) video_mixer (
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.clk_sys ( clk_50 ),
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.ce_pix ( clk_12p5 ),
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.ce_pix_actual ( clk_12p5 ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.SPI_DI ( SPI_DI ),
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.R ( {video,video,video}),
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.G ( {video,video,video}),
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.B ( {video,video,video}),
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.HSync ( hs ),
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.VSync ( vs ),
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.VGA_R ( VGA_R ),
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.VGA_G ( VGA_G ),
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.VGA_B ( VGA_B ),
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.VGA_VS ( VGA_VS ),
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.VGA_HS ( VGA_HS ),
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.scandoubler_disable(vid15khz ),
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.ypbpr_full ( 1 ),
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.line_start ( 0 ),
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.mono ( 1 )
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);
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mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io (
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.clk_sys ( clk_50 ),
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.conf_str ( CONF_STR ),
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.SPI_SCK ( SPI_SCK ),
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.CONF_DATA0 ( CONF_DATA0 ),
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.SPI_SS2 ( SPI_SS2 ),
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.SPI_DO ( SPI_DO ),
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.SPI_DI ( SPI_DI ),
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.buttons ( buttons ),
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.switches ( switches ),
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.scandoubler_disable(vid15khz ),
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.ypbpr ( ypbpr ),
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.ps2_kbd_clk ( ps2_kbd_clk ),
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.ps2_kbd_data ( ps2_kbd_data ),
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.status ( status )
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);
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endmodule
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