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101 lines
3.2 KiB
VHDL
101 lines
3.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Parametrizable, generic RAM with enable.
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--
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-- $Id: generic_ram_ena.vhd 295 2009-04-01 19:32:48Z arniml $
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity generic_ram_ena is
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generic (
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addr_width_g : integer := 10;
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data_width_g : integer := 8
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);
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port (
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clk_i : in std_logic;
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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we_i : in std_logic;
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ena_i : in std_logic;
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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end generic_ram_ena;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of generic_ram_ena is
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type mem_t is array (natural range 0 to 2**addr_width_g-1) of
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std_logic_vector(d_i'range);
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signal mem_q : mem_t
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-- pragma translate_off
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:= (others => (others => '0'))
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-- pragma translate_on
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;
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signal a_q : std_logic_vector(a_i'range);
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begin
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mem: process (clk_i)
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begin
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if clk_i'event and clk_i = '1' then
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if ena_i = '1' then
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if we_i = '1' then
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mem_q(to_integer(unsigned(a_i))) <= d_i;
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end if;
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a_q <= a_i;
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end if;
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end if;
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end process mem;
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d_o <= mem_q(to_integer(unsigned(a_q)));
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end rtl;
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