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38 lines
876 B
Verilog
38 lines
876 B
Verilog
/***************************************************************************************************
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* multiplier.v
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*
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***************************************************************************************************/
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module multiplier (
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input clk,
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input [17:0] a,
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input [17:0] b,
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output [35:0] p,
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output done
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);
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reg [17:0] old_a;
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reg [17:0] old_b;
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reg [35:0] shift_a;
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reg [35:0] product;
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reg [18:0] bindex;
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assign p = product;
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assign done = bindex[18];
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always @(posedge clk) begin
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if ((old_a != a) || (old_b != b)) begin
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bindex <= 19'h00001 << 1;
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product <= {18'h00000, b[0] ? a : 18'h00000};
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old_a <= a;
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old_b <= b;
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shift_a <= a << 1;
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end else if (bindex < 19'h40000) begin
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product <= product + ((bindex[17:0] & old_b) ? shift_a : 0);
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bindex <= bindex << 1;
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shift_a <= shift_a << 1;
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end
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end
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endmodule
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