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77 lines
1.7 KiB
VHDL
77 lines
1.7 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer: Erik Piehl
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--
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-- Create Date: 22:18:02 09/25/2017
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-- Design Name:
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-- Module Name: scartchpad - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY scratchpad IS
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GENERIC
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(
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widthad_a : natural := 7;
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width_a : natural := 16;
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outdata_reg_a : string := "UNREGISTERED"
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);
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PORT
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(
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addr : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clk : IN STD_LOGIC ;
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din : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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wr : IN STD_LOGIC ;
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dout : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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END scratchpad;
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ARCHITECTURE SYN OF scratchpad IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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BEGIN
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dout <= sub_wire0(width_a-1 DOWNTO 0);
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altsyncram_component : altsyncram
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GENERIC MAP (
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 2**widthad_a,
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operation_mode => "SINGLE_PORT",
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outdata_aclr_a => "NONE",
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outdata_reg_a => outdata_reg_a,
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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widthad_a => widthad_a,
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width_a => width_a,
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width_byteena_a => 1
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)
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PORT MAP (
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wren_a => wr,
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clock0 => clk,
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address_a => addr,
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data_a => din,
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q_a => sub_wire0
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);
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END SYN;
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