mirror of
https://github.com/Gehstock/Mist_FPGA.git
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130 lines
3.4 KiB
Verilog
130 lines
3.4 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 13-6-2020
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*/
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module jtopl_pg(
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input rst,
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input clk,
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input cenop,
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input [17:0] slot,
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input rhy_en,
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// Channel frequency
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input [ 9:0] fnum_I,
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input [ 2:0] block_I,
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// Operator multiplying
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input [ 3:0] mul_II,
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// phase modulation from LFO (vibrato at 6.4Hz)
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input [ 2:0] vib_cnt,
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input vib_dep,
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input viben_I,
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// phase operation
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input pg_rst_II,
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output reg [ 3:0] keycode_II,
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output [ 9:0] phase_IV
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);
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parameter CH=9;
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wire [ 3:0] keycode_I;
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wire [16:0] phinc_I;
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reg [16:0] phinc_II;
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wire [18:0] phase_drop, phase_in;
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wire [ 9:0] phase_II;
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wire noise;
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reg [ 9:0] hh, tc;
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reg rm_xor;
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wire hh_en, sd_en, tc_en;
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always @(posedge clk) if(cenop) begin
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keycode_II <= keycode_I;
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phinc_II <= phinc_I;
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end
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// Rhythm phase
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always @(posedge clk, posedge rst) begin
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if( rst ) begin
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hh <= 10'd0;
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tc <= 10'd0;
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end else begin
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if( slot[13] ) hh <= phase_drop[18:9];
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if( slot[17] ) tc <= phase_drop[18:9];
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rm_xor <= (hh[2]^hh[7]) | (hh[3]^tc[5]) | (tc[3]^tc[5]);
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end
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end
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assign hh_en = rhy_en & slot[14]; // 13+1
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assign sd_en = rhy_en & slot[17]; // 16+1
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assign tc_en = rhy_en & slot[ 0]; // (17+1)%18
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jtopl_noise u_noise(
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.clk ( clk ),
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.cen ( cenop ),
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.rst ( rst ),
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.noise ( noise )
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);
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jtopl_pg_comb u_comb(
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.block ( block_I ),
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.fnum ( fnum_I ),
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// Phase Modulation
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.vib_cnt ( vib_cnt ),
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.vib_dep ( vib_dep ),
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.viben ( viben_I ),
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.keycode ( keycode_I ),
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// Phase increment
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.phinc_out ( phinc_I ),
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// Phase add
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.mul ( mul_II ),
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.phase_in ( phase_drop ),
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.pg_rst ( pg_rst_II ),
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.phinc_in ( phinc_II ),
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// Rhythm
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.hh_en ( hh_en ),
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.sd_en ( sd_en ),
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.tc_en ( tc_en ),
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.rm_xor ( rm_xor ),
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.noise ( noise ),
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.hh ( hh ),
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.phase_out ( phase_in ),
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.phase_op ( phase_II )
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);
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jtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(
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.clk ( clk ),
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.cen ( cenop ),
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.rst ( rst ),
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.din ( phase_in ),
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.drop ( phase_drop)
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);
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jtopl_sh_rst #( .width(10), .stages(2) ) u_pad(
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.clk ( clk ),
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.cen ( cenop ),
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.rst ( rst ),
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.din ( phase_II ),
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.drop ( phase_IV )
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);
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endmodule
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