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140 lines
4.4 KiB
VHDL
140 lines
4.4 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- FPGA Lady Bug
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--
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-- $Id: ladybug_gpio.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $
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--
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-- General purpose IO input for CPU Main Unit.
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity ladybug_gpio is
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port (
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a_i : in std_logic_vector(1 downto 0);
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cs_in_n_i : in std_logic;
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cs_extra_n_i : in std_logic;
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in0_i : in std_logic_vector(7 downto 0);
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in1_i : in std_logic_vector(7 downto 0);
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in2_i : in std_logic_vector(7 downto 0);
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in3_i : in std_logic_vector(7 downto 0);
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extra_i : in std_logic_vector(7 downto 0);
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d_o : out std_logic_vector(7 downto 0)
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);
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end ladybug_gpio;
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architecture rtl of ladybug_gpio is
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begin
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-----------------------------------------------------------------------------
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-- Process gpio
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--
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-- Purpose:
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-- Multiplex the IN and EXTRA inputs onto the data bus for CPU.
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--
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gpio: process (a_i,
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cs_in_n_i,
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cs_extra_n_i,
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in0_i,
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in1_i,
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in2_i,
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in3_i,
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extra_i)
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variable cs_n_v : std_logic_vector(1 downto 0);
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begin
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-- default assignment with inactive bus value
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d_o <= (others => '1');
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cs_n_v := cs_extra_n_i & cs_in_n_i;
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case cs_n_v is
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-- IN ports and DIP switches selected -----------------------------------
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when "10" =>
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case a_i is
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-- IN 0 addressed
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when "00" =>
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d_o <= in0_i;
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-- IN 1 addressed
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when "01" =>
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d_o <= in1_i;
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-- DIP 0 addressed
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when "10" =>
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d_o <= in2_i;
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-- DIP 1 addressed
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when "11" =>
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d_o <= in3_i;
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when others =>
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null;
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end case;
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-- Extra bank selected --------------------------------------------------
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when "01" =>
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case a_i is
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when "00" =>
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d_o(1) <= extra_i(7);
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d_o(0) <= extra_i(3);
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when "01" =>
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d_o(1) <= extra_i(6);
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d_o(0) <= extra_i(2);
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when "10" =>
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d_o(1) <= extra_i(5);
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d_o(0) <= extra_i(1);
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when "11" =>
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d_o(1) <= extra_i(4);
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d_o(0) <= extra_i(0);
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when others =>
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null;
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end case;
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when others =>
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null;
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end case;
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end process gpio;
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--
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-----------------------------------------------------------------------------
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end rtl;
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