mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-09 17:51:09 +00:00
50 lines
1.5 KiB
Systemverilog
50 lines
1.5 KiB
Systemverilog
// Copyright Jamie Iles, 2017
|
|
//
|
|
// This file is part of s80x86.
|
|
//
|
|
// s80x86 is free software: you can redistribute it and/or modify
|
|
// it under the terms of the GNU General Public License as published by
|
|
// the Free Software Foundation, either version 3 of the License, or
|
|
// (at your option) any later version.
|
|
//
|
|
// s80x86 is distributed in the hope that it will be useful,
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
// GNU General Public License for more details.
|
|
//
|
|
// You should have received a copy of the GNU General Public License
|
|
// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
task do_ror;
|
|
output [31:0] out;
|
|
input is_8_bit;
|
|
input [15:0] a;
|
|
input [4:0] shift_count;
|
|
input [15:0] flags_in;
|
|
output [15:0] flags_out;
|
|
output busy;
|
|
input multibit_shift;
|
|
|
|
begin
|
|
flags_out = flags_in;
|
|
out = {11'b0, shift_count, a};
|
|
|
|
if (|shift_count || !multibit_shift) begin
|
|
if (!is_8_bit) begin
|
|
flags_out[CF_IDX] = a[0];
|
|
out[15:0] = {a[0], out[15:1]};
|
|
end else begin
|
|
flags_out[CF_IDX] = a[0];
|
|
out[7:0] = {a[0], out[7:1]};
|
|
end
|
|
|
|
flags_out[OF_IDX] = is_8_bit ? a[7] ^ a[0] : a[15] ^ a[0];
|
|
shift_flags(flags_out, is_8_bit, out[15:0], a);
|
|
|
|
out[31:16] = {11'b0, shift_count - 1'b1};
|
|
end
|
|
|
|
busy = multibit_shift && |out[20:16];
|
|
end
|
|
endtask
|