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59 lines
1.2 KiB
Verilog
59 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 20:44:36 04/25/2018
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// Design Name: LS175
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// Module Name: system86\src\ttl\ls175.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS175 - Quad D-Type Flip-Flop
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS175(
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input wire CLK,
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input wire CLR,
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input wire D1,
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input wire D2,
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input wire D3,
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input wire D4,
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output reg Q1,
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output wire Q1_L,
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output reg Q2,
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output wire Q2_L,
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output reg Q3,
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output wire Q3_L,
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output reg Q4,
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output wire Q4_L
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);
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always @(posedge CLK) begin
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if (CLR) begin
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Q1 <= 0;
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Q2 <= 0;
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Q3 <= 0;
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Q4 <= 0;
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end else begin
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Q1 <= D1;
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Q2 <= D2;
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Q3 <= D3;
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Q4 <= D4;
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end
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end
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assign Q1_L = ~Q1;
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assign Q2_L = ~Q2;
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assign Q3_L = ~Q3;
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assign Q4_L = ~Q4;
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endmodule
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