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23 lines
661 B
Systemverilog
23 lines
661 B
Systemverilog
// bin to one-hot, 4 bits to 16-bit bitmap
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module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap);
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always_comb begin
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case( bin)
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'b0000: bitMap = 16'h0001;
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'b0001: bitMap = 16'h0002;
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'b0010: bitMap = 16'h0004;
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'b0011: bitMap = 16'h0008;
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'b0100: bitMap = 16'h0010;
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'b0101: bitMap = 16'h0020;
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'b0110: bitMap = 16'h0040;
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'b0111: bitMap = 16'h0080;
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'b1000: bitMap = 16'h0100;
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'b1001: bitMap = 16'h0200;
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'b1010: bitMap = 16'h0400;
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'b1011: bitMap = 16'h0800;
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'b1100: bitMap = 16'h1000;
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'b1101: bitMap = 16'h2000;
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'b1110: bitMap = 16'h4000;
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'b1111: bitMap = 16'h8000;
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endcase
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end
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endmodule
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