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74 lines
948 B
Verilog
74 lines
948 B
Verilog
// based on TI SN74LS195 datasheet
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module SN74LS195(
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input clrn, //01
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input j, //02
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input kn, //03
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input a, //04
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input b, //05
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input c, //06
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input d, //07
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input sh_ldn, //09
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input clk, //10
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output qdn, //11
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output reg qd, //12
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output reg qc, //13
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output reg qb, //14
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output reg qa //15
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);
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always@(posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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qa <= 0;
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end
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else
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begin
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qa <= (~qa & j & sh_ldn) | (sh_ldn & kn & qa) | (~sh_ldn & a);
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end
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end
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always@(posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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qb <= 0;
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end
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else
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begin
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qb <= (qa & sh_ldn) | (~sh_ldn & b);
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end
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end
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always@(posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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qc <= 0;
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end
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else
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begin
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qc <= (qb & sh_ldn) | (~sh_ldn & c);
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end
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end
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always@(posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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qd <= 0;
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end
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else
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begin
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qd <= (qc & sh_ldn) | (~sh_ldn & d);
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end
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end
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assign qdn = ~qd;
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endmodule
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