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https://github.com/Gehstock/Mist_FPGA.git
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81 lines
1.8 KiB
VHDL
81 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.pace_pkg.all;
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use work.video_controller_pkg.all;
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use work.platform_pkg.all;
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--
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-- Asteroids Bitmap Controller
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--
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architecture BITMAP_1 of bitmapCtl is
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alias clk : std_logic is video_ctl.clk;
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alias clk_ena : std_logic is video_ctl.clk_ena;
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alias stb : std_logic is video_ctl.stb;
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alias hblank : std_logic is video_ctl.hblank;
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alias vblank : std_logic is video_ctl.vblank;
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alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x;
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alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y;
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alias rgb : RGB_t is ctl_o.rgb;
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begin
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-- these are constant for a whole line
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ctl_o.a(15) <= '0';
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ctl_o.a(14 downto 6) <= y(8 downto 0);
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-- generate pixel
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process (clk)
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variable pel : std_logic;
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begin
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if rising_edge(clk) and clk_ena = '1' then
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if hblank = '0' then
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-- 1st stage of pipeline
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-- - read bitmap data
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ctl_o.a(5 downto 0) <= x(8 downto 3);
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-- each byte contains information for 8 pixels
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case x(2 downto 0) is
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when "000" =>
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pel := ctl_i.d(6);
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when "001" =>
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pel := ctl_i.d(7);
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when "010" =>
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pel := ctl_i.d(0);
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when "011" =>
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pel := ctl_i.d(1);
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when "100" =>
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pel := ctl_i.d(2);
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when "101" =>
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pel := ctl_i.d(3);
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when "110" =>
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pel := ctl_i.d(4);
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when others =>
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pel := ctl_i.d(5);
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end case;
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-- slight blue tinge
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rgb.r <= (rgb.r'left-2 => '0', others => pel);
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rgb.g <= (rgb.g'left-2 => '0', others => pel);
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rgb.b <= (others => pel);
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end if; -- hblank = '0'
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end if;
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end process;
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ctl_o.set <= '1';
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end architecture BITMAP_1;
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