mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-25 00:07:31 +00:00
76 lines
1.7 KiB
VHDL
76 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.pace_pkg.all;
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entity inputmapper is
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generic
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(
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NUM_DIPS : integer := 8;
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NUM_INPUTS : integer := 2
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);
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port
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(
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clk : in std_logic;
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rst_n : in std_logic;
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-- inputs from keyboard controller
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reset : in std_logic;
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key_down : in std_logic;
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key_up : in std_logic;
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data : in std_logic_vector(7 downto 0);
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-- JAMMA interface
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jamma : in from_JAMMA_t;
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-- user outputs
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dips : in std_logic_vector(NUM_DIPS-1 downto 0);
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inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
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);
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end inputmapper;
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architecture SYN of inputmapper is
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begin
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latchInputs: process (clk, rst_n)
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variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
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begin
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-- note: all inputs are active LOW
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if rst_n = '0' then
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for i in 0 to NUM_INPUTS-2 loop
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jamma_v(i).d := (others =>'1');
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end loop;
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-- special keys
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jamma_v(NUM_INPUTS-1).d := (others => '1');
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elsif rising_edge (clk) then
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-- handle JAMMA inputs
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jamma_v(0).d(0) := jamma.p(1).up;
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jamma_v(1).d(0) := jamma.p(1).up;
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jamma_v(0).d(1) := jamma.p(1).down;
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jamma_v(1).d(1) := jamma.p(1).down;
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jamma_v(0).d(2) := jamma.p(1).left;
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jamma_v(1).d(2) := jamma.p(1).left;
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jamma_v(0).d(3) := jamma.p(1).right;
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jamma_v(1).d(3) := jamma.p(1).right;
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jamma_v(0).d(4) := jamma.coin(1);
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jamma_v(0).d(5) := jamma.coin(2);
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jamma_v(0).d(7) := jamma.p(1).button(1);
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jamma_v(1).d(4) := jamma.service;
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jamma_v(1).d(5) := jamma.p(1).start;
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jamma_v(1).d(6) := jamma.p(2).start;
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end if;
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end process latchInputs;
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end SYN;
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