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https://github.com/Gehstock/Mist_FPGA.git
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149 lines
4.7 KiB
VHDL
149 lines
4.7 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- FPGA Lady Bug
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--
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-- $Id: ladybug_res.vhd,v 1.8 2005/10/10 20:52:04 arnim Exp $
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--
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-- Reset generator for the Lady Bug machine.
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--
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-- This module generates a reset signal for the whole system synchronous to
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-- the main clock.
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity ladybug_res is
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port (
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clk_20mhz_i : in std_logic;
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ext_res_n_i : in std_logic;
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res_n_o : out std_logic;
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por_n_o : out std_logic
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);
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end ladybug_res;
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architecture rtl of ladybug_res is
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-- 4.7e-2 s = 1 / 20,000,000 Hz * 940000
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constant res_delay_c : natural := 940000;
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signal res_sync_n_q : std_logic_vector(1 downto 0);
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signal res_delay_q : unsigned(19 downto 0);
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signal res_n_q : std_logic;
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signal por_cnt_q : unsigned(1 downto 0) := "00";
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signal por_n_q : std_logic := '0';
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begin
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por_n_o <= por_n_q;
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res_n_o <= res_n_q;
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-----------------------------------------------------------------------------
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-- Process por_cnt
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--
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-- Purpose:
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-- Generate a power-on reset for 4 clock cycles.
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--
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por_cnt: process (clk_20mhz_i)
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begin
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if clk_20mhz_i'event and clk_20mhz_i = '1' then
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if por_cnt_q = "11" then
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por_n_q <= '1';
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else
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por_cnt_q <= por_cnt_q + 1;
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end if;
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end if;
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end process por_cnt;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process res_sync
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--
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-- Purpose:
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-- Synchronize asynchronous external reset to main 20 MHz clock.
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--
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res_sync: process (clk_20mhz_i, ext_res_n_i, por_n_q)
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begin
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if ext_res_n_i = '0' or por_n_q = '0' then
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res_sync_n_q <= (others => '0');
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elsif clk_20mhz_i'event and clk_20mhz_i = '1' then
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res_sync_n_q(0) <= '1';
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res_sync_n_q(1) <= res_sync_n_q(0);
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end if;
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end process res_sync;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process res_delay
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--
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-- Purpose:
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-- Delay reset event (external or power-on) by 4.7e-2 s.
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-- Reset delay is taken from Lady Bug reset circuit using NE555.
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-- This duration might be too long for the actual requirements of the
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-- FPGA circuit.
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--
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res_delay: process (clk_20mhz_i, res_sync_n_q)
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begin
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if res_sync_n_q(1) = '0' then
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res_delay_q <= (others => '0');
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res_n_q <= '0';
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elsif clk_20mhz_i'event and clk_20mhz_i = '1' then
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if res_delay_q = res_delay_c then
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res_n_q <= '1';
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else
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res_delay_q <= res_delay_q + 1;
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end if;
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end if;
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end process res_delay;
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--
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-----------------------------------------------------------------------------
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end rtl;
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