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88 lines
2.6 KiB
VHDL
88 lines
2.6 KiB
VHDL
--
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-- addmenux.vhd
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--
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-- Manage bus address multiplexer
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--
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-- Copyright (C)2001 - 2005 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: addmenux.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
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-- MODIFICATION :
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-- v0.01 : 200X/??/??
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-- v0.10 : 2009/06/25 : Intégration de la partie multiplexage de l'accès ram
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-- TODO :
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--
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-- TODO :
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-- Remark :
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_STD.all;
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--use IEEE.std_logic_unsigned.all;
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entity addmemux is
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port ( RESETn : in std_logic;
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VAP1 : in std_logic_vector(15 downto 0);-- Video address phase 1
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VAP2 : in std_logic_vector(15 downto 0);-- Video address phase 2
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BAP : in std_logic_vector(15 downto 0);-- Bus address processor (A15-A0)
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VA1L : in std_logic; -- Video address phase 1 LATCH
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VA1R : in std_logic; -- Video address phase 1 ROW
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VA1C : in std_logic; -- Video address phase 1 COLUMN
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VA2L : in std_logic; -- Video address phase 2 LATCH
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VA2R : in std_logic; -- Video address phase 2 ROW
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VA2C : in std_logic; -- Video address phase 2 COLUMN
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BAC : in std_logic; -- Bus address COLUMN
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BAL : in std_logic; -- Bus address LATCH
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AD_DYN : out std_logic_vector(15 downto 0) -- Address Bus dynamic
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);
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end entity addmemux;
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architecture addmemux_arch of addmemux is
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signal lVAP1 : std_logic_vector(15 downto 0);
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signal lVAP2 : std_logic_vector(15 downto 0);
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signal lBAP : std_logic_vector(15 downto 0);
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begin
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-- Latch VAP1
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u_VAP1 : PROCESS ( VAP1, VA1L,resetn )
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begin
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if (resetn = '0') then
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lVAP1 <= (OTHERS => '0');
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elsif rising_edge(VA1L) then
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lVAP1 <= VAP1;
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end if;
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end process;
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-- Latch VAP2
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u_VAP2 : PROCESS ( VAP2, VA2L, resetn )
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begin
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if (resetn = '0') then
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lVAP2 <= (OTHERS => '0');
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elsif rising_edge(VA2L) then
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lVAP2 <= VAP2;
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end if;
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end process;
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-- Latch BAP
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u_BAP: PROCESS ( BAP, BAL, resetn )
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begin
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if (resetn = '0') then
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lBAP<= (OTHERS => '0');
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elsif rising_edge(BAL) then
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lBAP<= BAP;
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end if;
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end process;
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-- Assignation
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AD_DYN <= lVAP1(15 downto 0) when VA1R = '1' else
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-- lVAP1(7 downto 0) when VA1C = '1' else
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lVAP2(15 downto 0) when VA2R = '1' else
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-- lVAP2(7 downto 0) when VA2C = '1' else
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-- lBAP when BAL = '1' else
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-- (OTHERS => 'Z');
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lBAP;
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end architecture addmemux_arch;
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