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126 lines
3.4 KiB
VHDL
126 lines
3.4 KiB
VHDL
--
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-- vag.vhd
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--
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-- Generate video signals
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--
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-- Copyright (C)2001 - 2005 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: vag.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
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--
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-- TODO :
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-- Remark :
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library IEEE;
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use IEEE.std_logic_1164.all;
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--use IEEE.std_logic_arith.all;
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--use IEEE.numeric_std.all;
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use IEEE.std_logic_unsigned.all;
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entity vag is
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port ( CLK_1 : in std_logic;
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RESETn : in std_logic;
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FREQ_SEL : in std_logic; -- Select 50/60 Hz frequency
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CPT_H : out std_logic_vector(6 downto 0); -- Horizontal Counter
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CPT_V : out std_logic_vector(8 downto 0); -- Vertical Counter
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RELOAD_SEL : out std_logic; -- Reload registe SEL
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FORCETXT : out std_logic; -- Force Mode Text
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CLK_FLASH : out std_logic; -- Flash Clock
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COMPSYNC : out std_logic; -- Composite Synchro signal
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BLANKINGn : out std_logic -- Blanking signal
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);
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end entity vag;
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architecture vag_arch of vag is
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signal lCPT_H : std_logic_vector(6 downto 0);
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signal lCPT_V : std_logic_vector(8 downto 0);
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signal lCPT_FLASH : std_logic_vector(5 downto 0);
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signal lVSYNCn : std_logic;
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signal lVBLANKn : std_logic;
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signal lVFRAME : std_logic;
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signal lFORCETXT : std_logic;
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signal lHSYNCn : std_logic;
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signal lHBLANKn : std_logic;
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signal lRELOAD_SEL : std_logic;
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signal lCLK_V : std_logic;
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begin
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-- Horizontal Counter
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u_CPT_H: PROCESS(CLK_1, RESETn)
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BEGIN
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IF (RESETn = '0') THEN
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lCPT_H <= (OTHERS => '0');
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ELSIF rising_edge(CLK_1) THEN
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IF lCPT_H < 63 then
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lCPT_H <= lCPT_H + "0000001";
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ELSE
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lCPT_H <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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-- Horizontal Synchronisation
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lHSYNCn <= '0' when (lCPT_H >= 49) AND (lCPT_H <= 53) ELSE '1';
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-- Horizontal Blank
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lHBLANKn <= '0' when (lCPT_H >= 40) AND (lCPT_H <= 63) ELSE '1';
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-- Signal to Reload Register to reset attribut
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lRELOAD_SEL <= '1' WHEN (lCPT_H >= 56) AND (lCPT_H <= 63) ELSE '0';
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-- Clock for Vertical counter
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lCLK_V <= '1' WHEN (lCPT_H = 63) ELSE '0';
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-- Vertical Counter
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u_CPT_V: PROCESS(lCLK_V, RESETn)
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BEGIN
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IF (RESETn = '0') THEN
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lCPT_V <= (OTHERS => '0');
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ELSIF rising_edge(lCLK_V) THEN
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IF (lCPT_V < 311) THEN
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lCPT_V <= lCPT_V + "000000001";
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ELSE
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lCPT_V <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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-- Vertical Synchronisation
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lVSYNCn <= '0' when(lCPT_V >= 258) AND (lCPT_V <= 259) ELSE '1';
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-- Vertical Blank
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lVBLANKn <= '0' when(lCPT_V >= 224) AND (lCPT_V <= 311) ELSE '1';
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-- Clock to Flash Counter
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lVFRAME <= '1' WHEN (lCPT_V = 311) ELSE '0';
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-- Signal To Force TEXT MODE
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lFORCETXT <= '1' WHEN (lCPT_V > 199) ELSE '0';
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-- Flash Counter
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u_FLASH : PROCESS( lVSYNCn, RESETn )
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BEGIN
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IF (RESETn = '0') THEN
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lCPT_FLASH <= (OTHERS => '0');
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ELSIF rising_edge(lVSYNCn) THEN
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lCPT_FLASH <= lCPT_FLASH + "000001";
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END IF;
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END PROCESS;
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-- Assign signals
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FORCETXT <= '1' WHEN ((lFORCETXT = '1') OR (lVFRAME = '1') ) ELSE '0';
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CLK_FLASH <= lCPT_FLASH(5);
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RELOAD_SEL <= lRELOAD_SEL;
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COMPSYNC <= NOT(lHSYNCn XOR lVSYNCn);
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-- Assign counters
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CPT_H <= lCPT_H;
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CPT_V <= lCPT_V;
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-- Assign blanking signal
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BLANKINGn <= lVBLANKn AND lHBLANKn;
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end architecture vag_arch;
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