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64 lines
701 B
Verilog
64 lines
701 B
Verilog
module SN74LS92(
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input clkb, //01
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input clra, //06
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input clrb, //07
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output reg qd, //08
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output reg qc, //09
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output reg qa, //12
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output reg qb, //13
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input clka //14
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);
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wire reset;
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assign reset = clra & clrb;
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always@(negedge clka or posedge reset)
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begin
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if (reset)
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begin
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qa <= 0;
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end
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else
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begin
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qa <= ~qa;
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end
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end
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always@(negedge clkb or posedge reset)
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begin
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if (reset)
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begin
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qb <= 0;
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end
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else
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begin
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qb <= ~(qb | qc);
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end
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end
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always@(negedge clkb or posedge reset)
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begin
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if (reset)
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begin
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qc <= 0;
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end
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else
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begin
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qc <= qb;
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end
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end
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always@(negedge clkb or posedge reset)
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begin
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if (reset)
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begin
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qd <= 0;
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end
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else
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begin
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qd <= qd ^ qc;
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end
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end
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endmodule
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