mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-25 20:11:30 +00:00
393 lines
12 KiB
VHDL
393 lines
12 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- $Id: t48_comp_pack-p.vhd,v 1.7 2004/06/30 21:16:21 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.alu_pack.alu_op_t;
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use work.cond_branch_pack.branch_conditions_t;
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use work.cond_branch_pack.comp_value_t;
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use work.decoder_pack.mnemonic_t;
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use work.dmem_ctrl_pack.dmem_addr_ident_t;
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use work.pmem_ctrl_pack.pmem_addr_ident_t;
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use work.t48_pack.dmem_addr_t;
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use work.t48_pack.pmem_addr_t;
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use work.t48_pack.mstate_t;
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use work.t48_pack.word_t;
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use work.t48_pack.nibble_t;
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package t48_comp_pack is
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component alu
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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data_o : out word_t;
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write_accu_i : in boolean;
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write_shadow_i : in boolean;
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write_temp_reg_i : in boolean;
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read_alu_i : in boolean;
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carry_i : in std_logic;
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carry_o : out std_logic;
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aux_carry_o : out std_logic;
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alu_op_i : in alu_op_t;
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use_carry_i : in boolean;
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da_high_i : in boolean;
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da_overflow_o : out boolean;
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accu_low_i : in boolean;
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p06_temp_reg_i : in boolean;
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p60_temp_reg_i : in boolean
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);
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end component;
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component bus_mux
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port (
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alu_data_i : in word_t;
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bus_data_i : in word_t;
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dec_data_i : in word_t;
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dm_data_i : in word_t;
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pm_data_i : in word_t;
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p1_data_i : in word_t;
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p2_data_i : in word_t;
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psw_data_i : in word_t;
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tim_data_i : in word_t;
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data_o : out word_t
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);
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end component;
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component clock_ctrl
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generic (
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xtal_div_3_g : integer := 1
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);
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port (
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clk_i : in std_logic;
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xtal_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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xtal3_o : out boolean;
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multi_cycle_i : in boolean;
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assert_psen_i : in boolean;
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assert_prog_i : in boolean;
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assert_rd_i : in boolean;
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assert_wr_i : in boolean;
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mstate_o : out mstate_t;
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second_cycle_o : out boolean;
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ale_o : out boolean;
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psen_o : out boolean;
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prog_o : out boolean;
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rd_o : out boolean;
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wr_o : out boolean
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);
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end component;
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component cond_branch
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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compute_take_i : in boolean;
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branch_cond_i : in branch_conditions_t;
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take_branch_o : out boolean;
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accu_i : in word_t;
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t0_i : in std_logic;
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t1_i : in std_logic;
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int_n_i : in std_logic;
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f0_i : in std_logic;
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f1_i : in std_logic;
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tf_i : in std_logic;
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carry_i : in std_logic;
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comp_value_i : in comp_value_t
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);
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end component;
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component db_bus
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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ea_i : in std_logic;
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data_i : in word_t;
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data_o : out word_t;
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write_bus_i : in boolean;
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read_bus_i : in boolean;
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output_pcl_i : in boolean;
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bidir_bus_i : in boolean;
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pcl_i : in word_t;
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db_i : in word_t;
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db_o : out word_t;
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db_dir_o : out std_logic
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);
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end component;
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component decoder
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generic (
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register_mnemonic_g : integer := 1
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);
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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ea_i : in std_logic;
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ale_i : in boolean;
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int_n_i : in std_logic;
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t0_dir_o : out std_logic;
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data_i : in word_t;
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data_o : out word_t;
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alu_write_accu_o : out boolean;
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alu_write_shadow_o : out boolean;
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alu_write_temp_reg_o : out boolean;
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alu_read_alu_o : out boolean;
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bus_write_bus_o : out boolean;
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bus_read_bus_o : out boolean;
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dm_write_dmem_addr_o : out boolean;
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dm_write_dmem_o : out boolean;
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dm_read_dmem_o : out boolean;
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p1_write_p1_o : out boolean;
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p1_read_p1_o : out boolean;
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p2_write_p2_o : out boolean;
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p2_write_exp_o : out boolean;
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p2_read_p2_o : out boolean;
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pm_write_pcl_o : out boolean;
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pm_read_pcl_o : out boolean;
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pm_write_pch_o : out boolean;
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pm_read_pch_o : out boolean;
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pm_read_pmem_o : out boolean;
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psw_read_psw_o : out boolean;
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psw_read_sp_o : out boolean;
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psw_write_psw_o : out boolean;
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psw_write_sp_o : out boolean;
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alu_carry_i : in std_logic;
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alu_op_o : out alu_op_t;
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alu_da_high_o : out boolean;
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alu_accu_low_o : out boolean;
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alu_da_overflow_i : in boolean;
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alu_p06_temp_reg_o : out boolean;
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alu_p60_temp_reg_o : out boolean;
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alu_use_carry_o : out boolean;
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bus_output_pcl_o : out boolean;
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bus_bidir_bus_o : out boolean;
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clk_multi_cycle_o : out boolean;
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clk_assert_psen_o : out boolean;
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clk_assert_prog_o : out boolean;
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clk_assert_rd_o : out boolean;
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clk_assert_wr_o : out boolean;
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clk_mstate_i : in mstate_t;
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clk_second_cycle_i : in boolean;
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cnd_compute_take_o : out boolean;
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cnd_branch_cond_o : out branch_conditions_t;
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cnd_take_branch_i : in boolean;
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cnd_comp_value_o : out comp_value_t;
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cnd_f1_o : out std_logic;
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cnd_tf_o : out std_logic;
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dm_addr_type_o : out dmem_addr_ident_t;
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tim_read_timer_o : out boolean;
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tim_write_timer_o : out boolean;
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tim_start_t_o : out boolean;
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tim_start_cnt_o : out boolean;
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tim_stop_tcnt_o : out boolean;
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p1_read_reg_o : out boolean;
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p2_read_reg_o : out boolean;
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p2_read_exp_o : out boolean;
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p2_output_pch_o : out boolean;
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p2_output_exp_o : out boolean;
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pm_inc_pc_o : out boolean;
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pm_write_pmem_addr_o : out boolean;
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pm_addr_type_o : out pmem_addr_ident_t;
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psw_special_data_o : out std_logic;
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psw_carry_i : in std_logic;
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psw_aux_carry_i : in std_logic;
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psw_f0_i : in std_logic;
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psw_inc_stackp_o : out boolean;
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psw_dec_stackp_o : out boolean;
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psw_write_carry_o : out boolean;
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psw_write_aux_carry_o : out boolean;
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psw_write_f0_o : out boolean;
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psw_write_bs_o : out boolean;
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tim_overflow_i : in boolean
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);
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end component;
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component dmem_ctrl
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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write_dmem_addr_i : in boolean;
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write_dmem_i : in boolean;
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read_dmem_i : in boolean;
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addr_type_i : in dmem_addr_ident_t;
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bank_select_i : in std_logic;
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data_o : out word_t;
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dmem_data_i : in word_t;
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dmem_addr_o : out dmem_addr_t;
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dmem_we_o : out std_logic;
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dmem_data_o : out word_t
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);
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end component;
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component int
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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clk_mstate_i : in mstate_t;
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jtf_executed_i : in boolean;
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tim_overflow_i : in boolean;
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tf_o : out std_logic;
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en_tcnti_i : in boolean;
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dis_tcnti_i : in boolean;
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int_n_i : in std_logic;
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ale_i : in boolean;
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last_cycle_i : in boolean;
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en_i_i : in boolean;
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dis_i_i : in boolean;
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ext_int_o : out boolean;
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tim_int_o : out boolean;
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retr_executed_i : in boolean;
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int_executed_i : in boolean;
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int_pending_o : out boolean;
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int_in_progress_o : out boolean
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);
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end component;
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component opc_table
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port (
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opcode_i : in word_t;
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multi_cycle_o : out std_logic;
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mnemonic_o : out mnemonic_t
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);
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end component;
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component opc_decoder
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generic (
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register_mnemonic_g : integer := 1
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);
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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read_bus_i : in boolean;
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inj_int_i : in boolean;
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opcode_o : out word_t;
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mnemonic_o : out mnemonic_t;
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multi_cycle_o : out boolean
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);
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end component;
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component timer
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generic (
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sample_t1_state_g : integer := 4
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);
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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t1_i : in std_logic;
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clk_mstate_i : in mstate_t;
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data_i : in word_t;
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data_o : out word_t;
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read_timer_i : in boolean;
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write_timer_i : in boolean;
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start_t_i : in boolean;
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start_cnt_i : in boolean;
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stop_tcnt_i : in boolean;
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overflow_o : out std_logic
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);
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end component;
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component p1
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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data_o : out word_t;
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write_p1_i : in boolean;
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read_p1_i : in boolean;
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read_reg_i : in boolean;
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p1_i : in word_t;
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p1_o : out word_t;
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p1_low_imp_o : out std_logic
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);
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end component;
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component p2
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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data_o : out word_t;
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write_p2_i : in boolean;
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write_exp_i : in boolean;
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read_p2_i : in boolean;
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read_reg_i : in boolean;
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read_exp_i : in boolean;
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output_pch_i : in boolean;
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output_exp_i : in boolean;
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pch_i : in nibble_t;
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p2_i : in word_t;
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p2_o : out word_t;
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p2_low_imp_o : out std_logic
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);
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end component;
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component pmem_ctrl
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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data_o : out word_t;
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write_pcl_i : in boolean;
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read_pcl_i : in boolean;
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write_pch_i : in boolean;
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read_pch_i : in boolean;
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inc_pc_i : in boolean;
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write_pmem_addr_i : in boolean;
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addr_type_i : in pmem_addr_ident_t;
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read_pmem_i : in boolean;
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pmem_addr_o : out pmem_addr_t;
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pmem_data_i : in word_t
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);
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end component;
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component psw
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port (
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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data_i : in word_t;
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data_o : out word_t;
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read_psw_i : in boolean;
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read_sp_i : in boolean;
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write_psw_i : in boolean;
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write_sp_i : in boolean;
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special_data_i : in std_logic;
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inc_stackp_i : in boolean;
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dec_stackp_i : in boolean;
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write_carry_i : in boolean;
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write_aux_carry_i : in boolean;
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write_f0_i : in boolean;
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write_bs_i : in boolean;
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carry_o : out std_logic;
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aux_carry_i : in std_logic;
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aux_carry_o : out std_logic;
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f0_o : out std_logic;
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bs_o : out std_logic
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);
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end component;
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end t48_comp_pack;
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