mirror of
https://github.com/Gehstock/Mist_FPGA.git
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189 lines
4.1 KiB
Systemverilog
189 lines
4.1 KiB
Systemverilog
module b2m_mist(
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input CLOCK_27,
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output LED,
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output SPI_DO,
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input SPI_DI,
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input SPI_SCK,
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input SPI_SS2,
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input SPI_SS3,
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input SPI_SS4,
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input CONF_DATA0,
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inout [15:0] SDRAM_DQ,
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output [12:0] SDRAM_A,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nWE,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nCS,
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output [1:0] SDRAM_BA,
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output SDRAM_CLK,
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output SDRAM_CKE,
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output AUDIO_L,
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output AUDIO_R,
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output VGA_HS,
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output VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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`include "rtl\build_id.v"
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localparam CONF_STR = {
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"Bashkiria 2M;;",
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"O2,Turbo ,ON,OFF;",
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"O3,Color Mode ,COLOR,B/W;",
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"O4,Video Mode ,PAL,NTSC;",
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"O56,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
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"T7,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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assign LED = 1'b1;
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assign AUDIO_R = AUDIO_L;
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wire clk_sys;
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire scandoublerD;
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wire ypbpr;
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wire ps2_kbd_clk;
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wire ps2_kbd_data;
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wire [15:0] audio;
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wire hs, vs;
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wire [3:0] r,g,b;
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pll pll(
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.inclk0(CLOCK_27),
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.c0(clk_sys),//50
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);
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b2m_top b2m_top(
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.clk50mhz(clk_sys),
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.res(~(status[0] | status[7] | buttons[1])),
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.color_mode(~status[3] ),
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.video_mode(status[4] ),
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.turbo(~status[2] ),
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.audio(audio),
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.DRAM_DQ(SDRAM_DQ),
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.DRAM_ADDR(SDRAM_A),
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.DRAM_LDQM(SDRAM_DQML),
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.DRAM_UDQM(SDRAM_DQMH),
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.DRAM_WE_N(SDRAM_nWE),
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.DRAM_CAS_N(SDRAM_nCAS),
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.DRAM_RAS_N(SDRAM_nRAS),
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.DRAM_CS_N(SDRAM_nCS),
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.DRAM_BA_0(SDRAM_BA[0]),
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.DRAM_BA_1(SDRAM_BA[1]),
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.DRAM_CLK(SDRAM_CLK),
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.DRAM_CKE(SDRAM_CKE),
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.VGA_HS(hs),
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.VGA_VS(vs),
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.VGA_R(r),
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.VGA_G(g),
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.VGA_B(b),
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.PS2_CLK(ps2_kbd_clk),
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.PS2_DAT(ps2_kbd_data),
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.SD_DAT(sd_sdo),
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.SD_DAT3(sd_cs),
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.SD_CMD(sd_sdi),
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.SD_CLK(sd_sck)
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);
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mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
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.clk_sys ( clk_sys ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.SPI_DI ( SPI_DI ),
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.R ( r),
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.G ( g),
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.B ( b),
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.HSync ( hs ),
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.VSync ( vs ),
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.VGA_R ( VGA_R ),
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.VGA_G ( VGA_G ),
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.VGA_B ( VGA_B ),
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.VGA_VS ( VGA_VS ),
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.VGA_HS ( VGA_HS ),
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.scandoubler_disable( 1'b1),//scandoublerD ),
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.scanlines ( status[6:5] ),
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.ce_divider (1),
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.ypbpr ( ypbpr )
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);
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user_io #(.STRLEN(($size(CONF_STR)>>3))) user_io(
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.clk_sys (clk_sys ),
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.conf_str (CONF_STR ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.buttons (buttons ),
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.switches (switches ),
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.scandoubler_disable (scandoublerD ),
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.ypbpr (ypbpr ),
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.ps2_kbd_clk (ps2_kbd_clk ),
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.ps2_kbd_data (ps2_kbd_data ),
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.status (status ),
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.sd_lba (sd_lba ),
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.sd_rd (sd_rd ),
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.sd_wr (sd_wr ),
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.sd_ack (sd_ack ),
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.sd_conf (sd_conf ),
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.sd_sdhc (sd_sdhc ),
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.sd_dout (sd_data_out ),
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.sd_din (sd_data_in ),
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.sd_dout_strobe (sd_data_in_strobe),
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.sd_din_strobe (sd_data_out_strobe)
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);
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dac #(
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.C_bits(16))
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dac(
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.clk_i(clk_sys),
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.res_n_i(1),
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.dac_i(audio),
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.dac_o(AUDIO_L)
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);
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wire [31:0] sd_lba;
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire sd_conf;
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wire sd_sdhc;
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wire allow_sdhc;
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wire [7:0] sd_data_in;
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wire sd_data_in_strobe;
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wire [7:0] sd_data_out;
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wire sd_data_out_strobe;
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wire sd_cs;
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wire sd_sck;
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wire sd_sdi;
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wire sd_sdo;
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sd_card sd_card(
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.io_lba (sd_lba),
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.io_rd (sd_rd),
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.io_wr (sd_wr),
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.io_ack (sd_ack),
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.io_conf (sd_conf),
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.io_sdhc (sd_sdhc),
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.io_din (sd_data_out),
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.io_din_strobe (sd_data_in_strobe),
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.io_dout (sd_data_in),
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.io_dout_strobe(sd_data_out_strobe),
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.allow_sdhc (allow_sdhc),
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.sd_cs (sd_cs),
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.sd_sck (sd_sck),
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.sd_sdi (sd_sdi),
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.sd_sdo (sd_sdo)
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);
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endmodule
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