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49 lines
1.2 KiB
VHDL
49 lines
1.2 KiB
VHDL
-- dualport-blockram für altera
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dualsram is
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generic(
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AddrWidth : integer := 11;
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DataWidth : integer := 8
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);
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port (
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clk1,clk2 : in std_logic;
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addr1, addr2 : in std_logic_vector(AddrWidth - 1 downto 0);
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din1, din2 : in std_logic_vector(DataWidth - 1 downto 0);
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dout1, dout2 : out std_logic_vector(DataWidth - 1 downto 0);
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we1_n, we2_n : in std_logic;
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ce1_n, ce2_n : in std_logic
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);
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end dualsram;
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architecture rtl of dualsram is
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type mem is array ((2 ** AddrWidth - 1) downto 0) of std_logic_vector(DataWidth - 1 downto 0);
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signal ram: mem := ((others=> (others=>'0')));
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begin
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process
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begin
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wait until rising_edge(clk1);
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if ce1_n = '0' and we1_n = '0' then
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ram(to_integer(unsigned(addr1))) <= din1;
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-- dout1 <= din1;
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end if;
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dout1 <= ram(to_integer(unsigned(addr1)));
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end process;
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process
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begin
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wait until rising_edge(clk2);
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if ce2_n = '0' and we2_n = '0' then
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ram(to_integer(unsigned(addr2))) <= din2;
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-- dout2 <= din2;
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end if;
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dout2 <= ram(to_integer(unsigned(addr2)));
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end process;
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end rtl; |