mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-18 13:26:54 +00:00
60 lines
2.1 KiB
VHDL
60 lines
2.1 KiB
VHDL
-- Copyright (c) 2015, $ME
|
|
-- All rights reserved.
|
|
--
|
|
-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
|
|
-- provided that the following conditions are met:
|
|
--
|
|
-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
|
|
-- and the following disclaimer.
|
|
--
|
|
-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
|
|
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
|
|
--
|
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
|
-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
|
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
|
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
|
-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
-- POSSIBILITY OF SUCH DAMAGE.
|
|
--
|
|
--
|
|
-- simple 8 bit parallel port
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
entity pport is
|
|
port (
|
|
clk : in std_logic;
|
|
|
|
ce_n : in std_logic; -- negative
|
|
wr_n : in std_logic; -- negative
|
|
res_n : in std_logic; -- negative
|
|
|
|
dIn : in std_logic_vector(7 downto 0);
|
|
|
|
pOut : out std_logic_vector(7 downto 0)
|
|
);
|
|
end pport;
|
|
|
|
architecture rtl of pport is
|
|
|
|
begin
|
|
process
|
|
begin
|
|
wait until rising_edge(clk);
|
|
|
|
if (ce_n='0' and wr_n='0') then
|
|
pOut <= dIn;
|
|
end if;
|
|
|
|
if (res_n='0') then
|
|
pOut <= (others => '0');
|
|
end if;
|
|
end process;
|
|
end;
|