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43 lines
1.0 KiB
VHDL
43 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity bootrom is
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port(
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clk : in std_logic;
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addr : in std_logic_vector(3 downto 0);
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data : out std_logic_vector(7 downto 0)
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);
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end bootrom;
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architecture rtl of bootrom is
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begin
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process
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begin
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wait until rising_edge(clk);
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case to_integer(unsigned(addr)) is
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when 0 => data <= x"C3"; -- JP F000
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when 1 => data <= x"00";
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when 2 => data <= x"F0";
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when others => data <= "--------";
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end case;
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-- case to_integer(unsigned(addr)) is
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-- when 0 => data <= x"F3"; -- DI
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-- when 1 => data <= x"31"; -- LD SP,200H
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-- when 2 => data <= x"00";
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-- when 3 => data <= x"02";
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-- when 4 => data <= x"C3"; -- JP 8000
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-- when 5 => data <= x"00";
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-- when 6 => data <= x"80";
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-- when others => data <= "--------";
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-- end case;
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end process;
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end;
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