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28 lines
916 B
Systemverilog
28 lines
916 B
Systemverilog
//
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// microrom and nanorom instantiation
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//
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// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed.
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// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance.
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// Might be more efficient to use vendor specific features such as clock enable.
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//
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module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput);
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reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH];
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initial begin
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$readmemb("microrom.mem", uRam);
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end
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always_ff @( posedge clk)
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microOutput <= uRam[ microAddr];
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endmodule
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module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput);
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reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH];
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initial begin
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$readmemb("nanorom.mem", nRam);
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end
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always_ff @( posedge clk)
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nanoOutput <= nRam[ nanoAddr];
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endmodule |