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68 lines
2.3 KiB
Systemverilog
68 lines
2.3 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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// Synchronize CS and IP updates so that they can be deployed to the
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// prefetcher atomically. For something like a far jump, the microcode would
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// first update the IP and then update CS. If this happens during the
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// microcode execution then potentially the prefetcher can start prefetching
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// from an invalid address - CS remains the same but IP changes and we fetch
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// from invalid/unmapped memory.
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//
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// This simple module just defers the output until propagation is ready, in
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// this case, on completion of the microinstruction when CS:IP can be
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// delivered to the prefetcher in a single cycle.
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`default_nettype none
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module CSIPSync(input logic clk,
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input logic reset,
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input logic cs_update,
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input logic ip_update,
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input logic [15:0] ip_in,
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input logic [15:0] new_ip,
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input logic propagate,
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output logic [15:0] ip_out,
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output logic update_out);
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reg [15:0] ip;
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reg ip_updated;
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reg cs_updated;
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assign ip_out = ip_updated ? ip : ip_update ? new_ip : ip_in;
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assign update_out = propagate &
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(ip_updated | cs_updated | cs_update | ip_update);
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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ip_updated <= 1'b0;
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cs_updated <= 1'b0;
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end else begin
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if (propagate) begin
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ip_updated <= 1'b0;
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cs_updated <= 1'b0;
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end
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if (ip_update && !ip_updated && !propagate) begin
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ip <= new_ip;
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ip_updated <= 1'b1;
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end
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if (cs_update && !propagate)
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cs_updated <= 1'b1;
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end
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end
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endmodule
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