mirror of
https://github.com/Gehstock/Mist_FPGA.git
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537 lines
20 KiB
Systemverilog
537 lines
20 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module Core(input logic clk,
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input logic reset,
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// Interrupts
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input logic nmi,
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input logic intr,
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input logic [7:0] irq,
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output logic inta,
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// Instruction bus
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output logic [19:1] instr_m_addr,
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input logic [15:0] instr_m_data_in,
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output logic instr_m_access,
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input logic instr_m_ack,
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// Data bus
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output logic [19:1] data_m_addr,
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input logic [15:0] data_m_data_in,
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output logic [15:0] data_m_data_out,
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output logic data_m_access,
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input logic data_m_ack,
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output logic data_m_wr_en,
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output logic [1:0] data_m_bytesel,
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output logic d_io,
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output logic lock,
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// Debug
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output logic debug_stopped,
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input logic debug_seize,
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input logic [7:0] debug_addr,
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input logic debug_run,
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output logic [15:0] debug_val,
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input logic [15:0] debug_wr_val,
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input logic debug_wr_en);
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// verilator lint_off UNUSED
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Instruction wr_instruction, cur_instruction, next_instruction_value;
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// verilator lint_on UNUSED
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// Internal busses.
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wire [15:0] a_bus =
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a_sel == ADriver_RA ? reg_rd_val[0] :
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a_sel == ADriver_IP ? ip_current :
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a_sel == ADriver_MAR ? mar : mdr;
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wire [15:0] b_bus =
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b_sel == BDriver_RB ? reg_rd_val[1] :
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b_sel == BDriver_IMMEDIATE ? immediate :
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b_sel == BDriver_IMMEDIATE2 ? cur_instruction.immediates[1] :
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b_sel == BDriver_SR ? seg_rd_val : tmp_val;
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// Register file.
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wire [15:0] si, di, bp, bx;
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wire reg_is_8_bit = is_8_bit;
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wire [2:0] reg_rd_sel[2];
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assign reg_rd_sel[0] = ra_modrm_rm_reg ? rm_regnum : microcode_reg_rd_sel[0];
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assign reg_rd_sel[1] = rb_cl ? CL : regnum;
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wire [2:0] reg_wr_sel =
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rd_sel_source == RDSelSource_MODRM_REG ? regnum :
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rd_sel_source == RDSelSource_MODRM_RM_REG ? rm_regnum :
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microcode_reg_wr_sel;
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wire [15:0] reg_wr_val =
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reg_wr_source == RegWrSource_Q ? alu_out[15:0] :
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reg_wr_source == RegWrSource_QUOTIENT ? quotient : remainder;
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wire reg_wr_en;
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wire [15:0] reg_rd_val[2];
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wire rb_cl;
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wire [`MC_RDSelSource_t_BITS-1:0] rd_sel_source;
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// Segment register file.
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wire io_operation;
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assign d_io = io_operation;
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wire segment_force;
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assign seg_wr_sel = segment_force ?
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microcode_segment : reg_wr_sel[1:0];
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wire [15:0] seg_rd_val;
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wire [15:0] seg_wr_val = alu_out[15:0];
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wire [15:0] cs;
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wire [1:0] segment;
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wire segment_wr_en;
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wire decode_immed_start;
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wire decode_immed_is_8bit;
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wire decode_fifo_rd_en;
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wire decode_complete;
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wire instruction_empty;
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wire instruction_fifo_full;
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wire instruction_fifo_nearly_full;
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// Prefetch FIFO
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wire fifo_wr_en;
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wire fifo_rd_en = immed_fifo_rd_en | decode_fifo_rd_en;
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wire [7:0] fifo_rd_data;
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wire [7:0] fifo_wr_data;
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wire fifo_empty;
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wire fifo_full;
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wire fifo_reset;
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// CS:IP Synchronizer
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wire cs_updating = seg_wr_sel == CS && segment_wr_en;
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wire [15:0] prefetch_cs = cs_updating ? seg_wr_val : cs;
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wire ip_wr_en;
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wire [15:0] ip_current;
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wire prefetch_load_new_ip;
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wire [15:0] prefetch_new_ip;
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// Immediate Reader
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wire immed_start = decode_immed_start;
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wire immed_complete;
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wire immed_is_8bit = decode_immed_is_8bit;
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wire [15:0] immediate_reader_immediate;
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wire [15:0] immediate = use_microcode_immediate ? microcode_immediate :
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cur_instruction.immediates[0];
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wire immed_fifo_rd_en;
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wire instruction_fifo_rd_en;
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// ModRM Decoder
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wire modrm_clear = reset | do_next_instruction | start_interrupt | fifo_reset;
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wire modrm_start;
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wire modrm_uses_bp_as_base;
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wire [2:0] regnum;
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wire rm_is_reg;
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wire [2:0] rm_regnum;
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wire ra_modrm_rm_reg;
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// Flags
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wire [15:0] flags;
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wire [8:0] update_flags;
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// LoadStore
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wire [15:0] mar;
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wire [15:0] mdr;
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wire microcode_write_mdr;
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wire write_mdr = microcode_write_mdr | irq_to_mdr;
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wire [15:0] mdr_in = microcode_write_mdr ? alu_out[15:0] : {8'b0, irq};
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wire microcode_write_mar;
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wire write_mar = microcode_write_mar & next_microinstruction;
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wire mem_read;
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wire mem_write;
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wire mar_wr_sel;
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wire [15:0] mar_wr_val;
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wire loadstore_start = (mem_read | mem_write) & ~loadstore_complete;
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wire loadstore_is_store = mem_write;
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wire loadstore_complete;
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wire loadstore_busy;
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assign mar_wr_val = mar_wr_sel == MARWrSel_EA ?
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effective_address : alu_out[15:0];
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// ALU
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wire [`MC_ALUOp_t_BITS-1:0] alu_op;
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wire [31:0] alu_out;
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wire [15:0] alu_flags_out;
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wire alu_busy;
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// Microcode
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wire [2:0] microcode_reg_rd_sel[2];
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wire [2:0] microcode_reg_wr_sel;
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wire [1:0] reg_wr_source;
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wire [1:0] seg_wr_sel;
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wire [1:0] a_sel;
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wire [2:0] b_sel;
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wire next_instruction;
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wire is_8_bit;
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wire [15:0] effective_address;
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wire microcode_tmp_wr_en;
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wire tmp_wr_en = microcode_tmp_wr_en | (debug_wr_en && debug_stopped);
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wire [15:0] tmp_wr_val = debug_stopped && debug_wr_en ? debug_wr_val :
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(tmp_wr_sel == TEMPWrSel_Q_LOW) ? alu_out[15:0] :
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alu_out[31:16];
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wire tmp_wr_sel;
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wire [15:0] tmp_val;
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wire [15:0] microcode_immediate;
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wire use_microcode_immediate;
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wire [1:0] microcode_segment;
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wire [7:0] opcode;
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wire jump_taken;
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wire multibit_shift;
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wire rb_zero = ~|reg_rd_val[1];
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wire nmi_pulse;
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wire ext_int_yield;
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wire irq_to_mdr;
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wire loop_next;
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wire loop_done;
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wire is_hlt;
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wire next_microinstruction;
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// Misc control signals
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wire debug_set_ip = debug_stopped && ip_wr_en;
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wire do_next_instruction = (next_instruction & ~do_stall) | debug_set_ip;
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wire do_stall = loadstore_busy | divide_busy | alu_busy;
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wire start_interrupt;
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// IP
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wire do_escape_fault;
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wire starting_instruction;
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wire ip_rollback = (start_interrupt & ext_int_yield & ~is_hlt) | do_escape_fault;
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// Divider
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wire [31:0] dividend8 = divide_signed ? {{16{tmp_val[15]}}, tmp_val} : {16'b0, tmp_val};
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wire [31:0] dividend = is_8_bit ? dividend8 : {reg_rd_val[0], tmp_val};
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wire [15:0] divisor8 = divide_signed ? {{8{mdr[7]}}, mdr[7:0]} : mdr;
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wire [15:0] divisor = is_8_bit ? divisor8 : mdr;
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wire [15:0] quotient;
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wire [15:0] remainder;
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wire divide_error;
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wire divide_busy;
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wire divide = alu_op == ALUOp_DIV || alu_op == ALUOp_IDIV;
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wire divide_signed = alu_op == ALUOp_IDIV;
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wire divide_complete;
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wire do_divide = divide & ~divide_complete;
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assign debug_val = tmp_val;
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RegisterFile RegisterFile(.clk(clk),
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.reset(reset),
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.si(si),
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.di(di),
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.bp(bp),
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.bx(bx),
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.is_8_bit(reg_is_8_bit),
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.rd_sel(reg_rd_sel),
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.rd_val(reg_rd_val),
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.wr_sel(reg_wr_sel),
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.wr_val(reg_wr_val),
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.wr_en(reg_wr_en));
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SegmentOverride SegmentOverride(.clk(clk),
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.reset(reset),
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.flush(fifo_reset),
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.next_instruction(do_next_instruction),
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.force_segment(segment_force),
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.bp_is_base(modrm_uses_bp_as_base),
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.update(starting_instruction),
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.segment_override(next_instruction_value.has_segment_override),
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.override_in(next_instruction_value.segment),
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.microcode_sr_rd_sel(microcode_segment),
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.sr_rd_sel(segment));
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SegmentRegisterFile SegmentRegisterFile(.clk(clk),
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.reset(reset),
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.rd_sel(segment),
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.rd_val(seg_rd_val),
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.wr_en(segment_wr_en),
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.wr_sel(seg_wr_sel),
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.wr_val(seg_wr_val),
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.cs(cs));
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Fifo #(.data_width(8),
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.depth(6))
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PrefetchFifo(.clk(clk),
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.reset(reset),
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.flush(fifo_reset),
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.wr_en(fifo_wr_en),
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.wr_data(fifo_wr_data),
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.rd_en(fifo_rd_en),
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.rd_data(fifo_rd_data),
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.empty(fifo_empty),
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.nearly_full(fifo_full),
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// verilator lint_off PINCONNECTEMPTY
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.full()
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// verilator lint_on PINCONNECTEMPTY
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);
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CSIPSync CSIPSync(.clk(clk),
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.reset(reset),
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.cs_update(cs_updating),
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.ip_update(ip_wr_en),
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.ip_in(ip_current),
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.new_ip(alu_out[15:0]),
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.propagate(do_next_instruction),
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.ip_out(prefetch_new_ip),
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.update_out(prefetch_load_new_ip));
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TempReg TempReg(.clk(clk),
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.reset(reset),
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.wr_val(tmp_wr_val),
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.wr_en(tmp_wr_en),
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.val(tmp_val));
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Prefetch Prefetch(.clk(clk),
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.reset(reset),
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.new_cs(prefetch_cs),
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.new_ip(prefetch_new_ip),
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.load_new_ip(prefetch_load_new_ip),
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.fifo_wr_en(fifo_wr_en),
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.fifo_wr_data(fifo_wr_data),
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.fifo_reset(fifo_reset),
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.fifo_full(fifo_full),
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.mem_access(instr_m_access),
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.mem_ack(instr_m_ack),
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.mem_address(instr_m_addr),
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.mem_data(instr_m_data_in));
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ImmediateReader ImmediateReader(.clk(clk),
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.reset(reset),
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// Control
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.start(immed_start),
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.flush(fifo_reset),
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// verilator lint_off PINCONNECTEMPTY
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.busy(),
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// verilator lint_on PINCONNECTEMPTY
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.complete(immed_complete),
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.is_8bit(immed_is_8bit),
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// Result
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.immediate(immediate_reader_immediate),
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// Fifo read port
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.fifo_rd_en(immed_fifo_rd_en),
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.fifo_rd_data(fifo_rd_data),
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.fifo_empty(fifo_empty));
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LoopCounter LoopCounter(.clk(clk),
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.count_in(next_instruction_value.immediates[1][4:0]),
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.load(instruction_fifo_rd_en),
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.next(loop_next),
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.done(loop_done));
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Fifo #(.data_width($bits(Instruction)),
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.depth(4),
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.full_threshold(1))
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InstructionFifo(.clk(clk),
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.reset(reset),
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.flush(fifo_reset),
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.wr_en(decode_complete),
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.wr_data(wr_instruction),
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.rd_en(instruction_fifo_rd_en),
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.rd_data(next_instruction_value),
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.empty(instruction_empty),
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.nearly_full(instruction_fifo_nearly_full),
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.full(instruction_fifo_full));
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InsnDecoder InsnDecoder(.clk(clk),
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.reset(reset),
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.flush(fifo_reset),
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.stall(instruction_fifo_full),
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.nearly_full(instruction_fifo_nearly_full),
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.fifo_rd_en(decode_fifo_rd_en),
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.fifo_rd_data(fifo_rd_data),
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.fifo_empty(fifo_empty),
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.instruction(wr_instruction),
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.complete(decode_complete),
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.immed_start(decode_immed_start),
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.immed_complete(immed_complete),
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.immed_is_8bit(decode_immed_is_8bit),
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.immediate(immediate_reader_immediate));
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ModRMDecode ModRMDecode(.clk(clk),
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.reset(reset),
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.si(si),
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.di(di),
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.bp(bp),
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.bx(bx),
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// Control
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.start(modrm_start),
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.clear(modrm_clear),
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.modrm(next_instruction_value.mod_rm),
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.displacement(next_instruction_value.displacement),
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// Results
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.effective_address(effective_address),
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.regnum(regnum),
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.rm_is_reg(rm_is_reg),
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.rm_regnum(rm_regnum),
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.bp_as_base(modrm_uses_bp_as_base));
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Flags Flags(.clk(clk),
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.reset(reset),
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.flags_in(alu_flags_out),
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.flags_out(flags),
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.update_flags(update_flags));
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JumpTest JumpTest(.opcode(opcode),
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.flags(flags),
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.taken(jump_taken));
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LoadStore LoadStore(.clk(clk),
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.reset(reset),
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// MAR
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.write_mar(write_mar),
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.segment(seg_rd_val),
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.mar_in(mar_wr_val),
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// MDR
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.mar_out(mar),
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.mdr_out(mdr),
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.write_mdr(write_mdr),
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.mdr_in(mdr_in),
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// Memory bus
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.m_addr(data_m_addr),
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.m_data_in(data_m_data_in),
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.m_data_out(data_m_data_out),
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.m_access(data_m_access),
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.m_ack(data_m_ack),
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.m_wr_en(data_m_wr_en),
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.m_bytesel(data_m_bytesel),
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// Control
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.start(loadstore_start),
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.is_8bit(is_8_bit),
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.wr_en(loadstore_is_store),
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.busy(loadstore_busy),
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.complete(loadstore_complete),
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.io(io_operation));
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PosedgeToPulse PosedgeToPulse(.d(nmi),
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.q(nmi_pulse),
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.*);
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Microcode Microcode(.clk(clk),
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.reset(reset),
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.nmi_pulse(nmi_pulse),
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.intr(intr),
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.inta(inta),
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.irq_to_mdr(irq_to_mdr),
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.start_interrupt(start_interrupt),
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.do_escape_fault(do_escape_fault),
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.starting_instruction(starting_instruction),
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.stall(do_stall),
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.divide_error(divide_error),
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.modrm_reg(regnum),
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.int_enabled(flags[IF_IDX]),
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.zf(flags[ZF_IDX]),
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.tf(flags[TF_IDX]),
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.microcode_immediate(microcode_immediate),
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.use_microcode_immediate(use_microcode_immediate),
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.opcode(opcode),
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.jump_taken(jump_taken),
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.rb_zero(rb_zero),
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.lock(lock),
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.multibit_shift(multibit_shift),
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.rm_is_reg(rm_is_reg),
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.a_sel(a_sel),
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.alu_op(alu_op),
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.b_sel(b_sel),
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.ext_int_yield(ext_int_yield),
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.io(io_operation),
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.next_instruction(next_instruction),
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.load_ip(ip_wr_en),
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.mar_wr_sel(mar_wr_sel),
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.mar_write(microcode_write_mar),
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.mdr_write(microcode_write_mdr),
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.mem_read(mem_read),
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.mem_write(mem_write),
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.modrm_start(modrm_start),
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.ra_modrm_rm_reg(ra_modrm_rm_reg),
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.ra_sel(microcode_reg_rd_sel[0]),
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.rb_cl(rb_cl),
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.rd_sel_source(rd_sel_source),
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.rd_sel(microcode_reg_wr_sel),
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.reg_wr_en(reg_wr_en),
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.reg_wr_source(reg_wr_source),
|
|
.segment(microcode_segment),
|
|
.segment_force(segment_force),
|
|
.segment_wr_en(segment_wr_en),
|
|
.tmp_wr_en(microcode_tmp_wr_en),
|
|
.tmp_wr_sel(tmp_wr_sel),
|
|
.update_flags(update_flags),
|
|
.width(is_8_bit),
|
|
.fifo_rd_en(instruction_fifo_rd_en),
|
|
.cur_instruction(cur_instruction),
|
|
.next_instruction_value(next_instruction_value),
|
|
.fifo_empty(instruction_empty),
|
|
.fifo_resetting(fifo_reset),
|
|
.loop_next(loop_next),
|
|
.loop_done(loop_done),
|
|
.is_hlt(is_hlt),
|
|
.next_microinstruction(next_microinstruction),
|
|
// Debug
|
|
.debug_stopped(debug_stopped),
|
|
.debug_seize(debug_seize),
|
|
.debug_addr(debug_addr),
|
|
.debug_run(debug_run));
|
|
|
|
IP IP(.clk(clk),
|
|
.reset(reset),
|
|
.inc(next_instruction_value.length),
|
|
.start_instruction(instruction_fifo_rd_en),
|
|
.next_instruction(do_next_instruction),
|
|
.rollback(ip_rollback),
|
|
.wr_en(prefetch_load_new_ip),
|
|
.wr_val(prefetch_new_ip),
|
|
.val(ip_current));
|
|
|
|
ALU ALU(.a(a_bus),
|
|
.b(b_bus),
|
|
.out(alu_out),
|
|
.op(alu_op),
|
|
.is_8_bit(is_8_bit),
|
|
.flags_in(flags),
|
|
.flags_out(alu_flags_out),
|
|
.multibit_shift(multibit_shift),
|
|
.shift_count(tmp_val[4:0]),
|
|
.busy(alu_busy));
|
|
|
|
Divider Divider(.clk(clk),
|
|
.reset(reset),
|
|
.start(do_divide),
|
|
.is_8_bit(is_8_bit),
|
|
.is_signed(divide_signed),
|
|
.busy(divide_busy),
|
|
.complete(divide_complete),
|
|
.error(divide_error),
|
|
.dividend(dividend),
|
|
.divisor(divisor),
|
|
.quotient(quotient),
|
|
.remainder(remainder));
|
|
|
|
`ifdef verilator
|
|
// verilator lint_off BLKANDNBLK
|
|
int instr_length;
|
|
// verilator lint_on BLKANDNBLK
|
|
|
|
always @(posedge clk)
|
|
if (instruction_fifo_rd_en)
|
|
instr_length <= {28'b0, next_instruction_value.length};
|
|
|
|
export "DPI-C" function get_and_clear_instr_length;
|
|
|
|
function int get_and_clear_instr_length;
|
|
get_and_clear_instr_length = instr_length;
|
|
instr_length = 0;
|
|
endfunction
|
|
|
|
`endif
|
|
|
|
endmodule
|