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104 lines
3.6 KiB
Systemverilog
104 lines
3.6 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module ModRMDecode(input logic clk,
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input logic reset,
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// Control.
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input logic start,
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input logic clear,
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input logic [7:0] modrm,
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input logic [15:0] displacement,
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input logic [15:0] si,
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input logic [15:0] di,
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input logic [15:0] bp,
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input logic [15:0] bx,
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// Results
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output logic [15:0] effective_address,
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output logic [2:0] regnum,
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output logic rm_is_reg,
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output logic [2:0] rm_regnum,
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output logic bp_as_base);
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wire [1:0] _mod = modrm[7:6];
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wire [2:0] _reg = modrm[5:3];
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wire [2:0] _rm = modrm[2:0];
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always_ff @(posedge clk or posedge reset) begin
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if (reset) begin
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bp_as_base <= 1'b0;
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rm_is_reg <= 1'b0;
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regnum <= 3'b0;
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rm_regnum <= 3'b0;
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end else begin
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if (clear)
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bp_as_base <= 1'b0;
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if (start) begin
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regnum <= _reg;
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rm_regnum <= _rm;
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rm_is_reg <= _mod == 2'b11;
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case (_mod)
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2'b00: bp_as_base <= (_rm == 3'b010 || _rm == 3'b011);
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2'b01: bp_as_base <= (_rm == 3'b010 || _rm == 3'b011 || _rm == 3'b110);
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2'b10: bp_as_base <= (_rm == 3'b010 || _rm == 3'b011 || _rm == 3'b110);
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default: bp_as_base <= 1'b0;
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endcase
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end
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end
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end
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always_ff @(posedge clk or posedge reset) begin
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if (reset)
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effective_address <= 16'b0;
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else begin
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if (start) begin
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effective_address <= 16'b0;
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case (_mod)
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2'b00: begin
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case (_rm)
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3'd0: effective_address <= bx + si;
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3'd1: effective_address <= bx + di;
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3'd2: effective_address <= bp + si;
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3'd3: effective_address <= bp + di;
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3'd4: effective_address <= si;
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3'd5: effective_address <= di;
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3'd6: effective_address <= displacement;
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3'd7: effective_address <= bx;
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endcase
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end
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2'b01, 2'b10: begin
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case (_rm)
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3'd0: effective_address <= bx + si + displacement;
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3'd1: effective_address <= bx + di + displacement;
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3'd2: effective_address <= bp + si + displacement;
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3'd3: effective_address <= bp + di + displacement;
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3'd4: effective_address <= si + displacement;
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3'd5: effective_address <= di + displacement;
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3'd6: effective_address <= bp + displacement;
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3'd7: effective_address <= bx + displacement;
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endcase
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end
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2'b11: effective_address <= 16'b0;
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endcase
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end
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end
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end
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endmodule
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