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97 lines
4.1 KiB
Systemverilog
97 lines
4.1 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module ALU(input logic [15:0] a,
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input logic [15:0] b,
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output logic [31:0] out,
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input logic is_8_bit,
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input logic [`MC_ALUOp_t_BITS-1:0] op,
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input logic [15:0] flags_in,
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output logic [15:0] flags_out,
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input logic multibit_shift,
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input logic [4:0] shift_count,
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output logic busy);
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always_comb begin
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flags_out = flags_in;
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out = 32'b0;
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busy = 1'b0;
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case (op)
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ALUOp_SELA: out[15:0] = a;
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ALUOp_SELB: out[15:0] = b;
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ALUOp_ADD: do_add(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_ADC: do_adc(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_AND: do_and(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_XOR: do_xor(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_OR: do_or(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_BOUNDH: do_bound(a, b, flags_in, flags_out);
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ALUOp_BOUNDL: do_bound(b, a, flags_in, flags_out);
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ALUOp_SUB: do_sub(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_SUBREV: do_sub(out[15:0], is_8_bit, b, a, flags_in, flags_out);
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ALUOp_SBB: do_sbb(out[15:0], is_8_bit, a, b, flags_in, flags_out);
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ALUOp_SBBREV: do_sbb(out[15:0], is_8_bit, b, a, flags_in, flags_out);
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ALUOp_ENTER_FRAME_TEMP_ADDR: do_enter_frame_temp_addr(out[15:0], a, b[4:0]);
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ALUOp_GETFLAGS: out[15:0] = flags_in;
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ALUOp_SETFLAGSA: flags_out = a;
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ALUOp_SETFLAGSB: flags_out = b;
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ALUOp_CMC: flags_out[CF_IDX] = ~flags_in[CF_IDX];
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ALUOp_SHR: do_shr(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_SHL: do_shl(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_SAR: do_sar(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_ROR: do_ror(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_ROL: do_rol(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_RCL: do_rcl(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_RCR: do_rcr(out, is_8_bit, a, shift_count, flags_in, flags_out, busy,
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multibit_shift);
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ALUOp_NOT: do_not(out[15:0], a, flags_in, flags_out);
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ALUOp_AAA: do_aaa(out[15:0], a, flags_in, flags_out);
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ALUOp_AAS: do_aas(out[15:0], a, flags_in, flags_out);
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ALUOp_DAA: do_daa(out[15:0], a, flags_in, flags_out);
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ALUOp_DAS: do_das(out[15:0], a, flags_in, flags_out);
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ALUOp_MUL: do_mul(out, is_8_bit, a, b, flags_in, flags_out, 1'b0);
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ALUOp_IMUL: do_mul(out, is_8_bit, a, b, flags_in, flags_out, 1'b1);
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ALUOp_EXTEND: do_extend(out[15:0], is_8_bit, a);
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ALUOp_DIV: ; // Handled by Divider, shares the enumeration.
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ALUOp_IDIV: ; // Handled by Divider, shares the enumeration.
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ALUOp_NEXT: begin
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if (flags_in[DF_IDX])
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do_sub(out[15:0], 1'b0, a, b, flags_in, flags_out);
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else
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do_add(out[15:0], 1'b0, a, b, flags_in, flags_out);
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end
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// verilator coverage_off
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default: begin
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`ifdef verilator
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invalid_opcode_assertion: assert(0) begin
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$display("oops!");
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end
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`endif // verilator
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end
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// verilator coverage_on
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endcase
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end
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endmodule
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