mirror of
https://github.com/Gehstock/Mist_FPGA.git
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82 lines
3.3 KiB
Plaintext
82 lines
3.3 KiB
Plaintext
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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.at 0xe8;
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jmp calle8, ra_sel SP;
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.auto_address;
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calle8:
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q;
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a_sel IP, alu_op SELA, mdr_write, ra_sel SP, segment SS, segment_force;
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segment SS, segment_force, mem_write, a_sel IP, b_sel IMMEDIATE,
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alu_op ADD, load_ip, next_instruction;
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callff_indirect_intra_reg:
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a_sel RA, alu_op SELA, load_ip, jmp callff_indirect_intra_save,
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ra_sel SP;
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callff_indirect_intra_mem:
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segment DS, mem_read;
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a_sel MDR, alu_op SELA, load_ip, jmp callff_indirect_intra_save,
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ra_sel SP;
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callff_indirect_intra_save:
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q;
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a_sel IP, alu_op SELA, mdr_write, ra_sel SP, segment SS, segment_force;
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segment SS, segment_force, mem_write, next_instruction;
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.at 0x9a;
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jmp call9a, mdr_write, b_sel IMMEDIATE, alu_op SELB,
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alu_op SELB, load_ip, segment CS;
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.auto_address;
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call9a:
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b_sel SR, alu_op SELB, mdr_write, ra_sel SP;
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q, segment_force, segment SS;
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segment_force, segment SS, mem_write, ra_sel SP;
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q;
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a_sel IP, alu_op SELA, mdr_write, segment_force, segment SS;
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segment_force, segment SS, mem_write;
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b_sel IMMEDIATE2, alu_op SELB, segment_force, segment CS,
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segment_wr_en, next_instruction;
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callff_indirect_inter_reg:
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next_instruction;
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callff_indirect_inter_mem:
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b_sel SR, alu_op SELB, mdr_write, ra_sel SP;
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q, segment_force, segment SS;
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segment_force, segment SS, mem_write, ra_sel SP;
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a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,
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rd_sel_source MICROCODE_RD_SEL, mar_write,
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mar_wr_sel Q;
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a_sel IP, alu_op SELA, mdr_write, segment_force, segment SS;
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segment_force, segment SS, mem_write;
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mar_wr_sel EA, mar_write, segment DS;
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segment DS, mem_read;
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a_sel MDR, alu_op SELA, load_ip;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op ADD,
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mar_wr_sel Q, mar_write, segment DS;
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segment DS, mem_read;
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a_sel MDR, alu_op SELA, segment_wr_en,
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segment_force, segment CS, next_instruction;
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