mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-18 17:06:57 +00:00
292 lines
11 KiB
Plaintext
292 lines
11 KiB
Plaintext
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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#include <config.h>
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.at 0x100;
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opcode_fetch:
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ext_int_yield, jmp_opcode;
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// See 0xcc in int.us for more details, this is the same thing but for a
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// divide error.
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.at 0x101;
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divide_error:
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b_sel IMMEDIATE, immediate 0x0, alu_op SELB, tmp_wr_en, jmp do_int;
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// See 0xcc in int.us for more details, this is the same thing but for a
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// IRQ.
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.at 0x12b;
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// IRQ number to temp
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a_sel MDR, b_sel IMMEDIATE, immediate 0x4, alu_op MUL, tmp_wr_en,
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jmp do_int;
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// See 0xcc in int.us for more details, this is the same thing but for a
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// NMI.
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.at 0x12a;
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nmi:
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b_sel IMMEDIATE, immediate 0x8, alu_op SELB, tmp_wr_en, jmp do_int;
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// See 0xcc in int.us for more details, this is the same thing but for a
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// single step trap.
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.at 0x12c;
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single_step:
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b_sel IMMEDIATE, immediate 0x4, alu_op SELB, tmp_wr_en, jmp do_int;
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// Wait a single cycle for modrm decoding to complete
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.at 0x12e;
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modrm_decode:
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jmp_opcode;
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.at 0x12f;
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bad_opcode:
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jmp invalid_opcode;
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#define INVALID_OPCODE(opc) \
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.at opc; \
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jmp invalid_opcode
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#define FILL(opc) \
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.at opc; \
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next_instruction
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INVALID_OPCODE(0x0f);
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INVALID_OPCODE(0x63);
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INVALID_OPCODE(0x64);
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INVALID_OPCODE(0x65);
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INVALID_OPCODE(0x66);
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INVALID_OPCODE(0x67);
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INVALID_OPCODE(0xf1);
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FILL(0x26);
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FILL(0x2e);
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FILL(0x36);
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FILL(0x3e);
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FILL(0xf0);
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FILL(0xf2);
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FILL(0xf3);
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.auto_address;
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invalid_opcode:
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b_sel IMMEDIATE, immediate 0x18, alu_op SELB, tmp_wr_en, jmp do_int;
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// Multiplexed add/adc/sub/sbb/cmp/xor/or/and
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// r/m OP immed8
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.at 0x80;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_80_81;
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.auto_address;
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dispatch_80_81:
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem ADD80_81_reg; // reg == 0
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem OR80_81_reg; // reg == 1
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem ADC80_81_reg; // reg == 2
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SBB80_81_reg; // reg == 3
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem AND80_81_reg; // reg == 4
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SUB80_81_reg; // reg == 5
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem XOR80_81_reg; // reg == 6
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem compSUB80_81_reg; // reg == 7
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// Multiplexed add/adc/sub/sbb/cmp/xor/or/and
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// r/m OP immed16
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.at 0x81;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_80_81;
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// Multiplexed add/adc/sub/sbb/cmp
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// r/m OP immed8
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.at 0x82;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_80_81;
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// Multiplexed add/adc/sub/sbb/cmp/xor/or/and
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// r/m OP immed16
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.at 0x83;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_83;
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.auto_address;
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dispatch_83:
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segment DS, jmp_rm_reg_mem ADD83_reg; // reg == 0
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segment DS, jmp_rm_reg_mem OR83_reg; // reg == 1
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segment DS, jmp_rm_reg_mem ADC83_reg; // reg == 2
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segment DS, jmp_rm_reg_mem SBB83_reg; // reg == 3
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segment DS, jmp_rm_reg_mem AND83_reg; // reg == 4
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segment DS, jmp_rm_reg_mem SUB83_reg; // reg == 5
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segment DS, jmp_rm_reg_mem XOR83_reg; // reg == 6
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segment DS, jmp_rm_reg_mem compSUB83_reg; // reg == 7
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// Multiplexed pop/8f
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.at 0x8f;
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mar_write, mar_wr_sel EA, segment SS, jmp_dispatch_reg dispatch_8f;
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.auto_address;
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dispatch_8f:
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ra_sel SP, jmp_rm_reg_mem pop8f_reg; // reg == 0
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next_instruction; // reg == 1
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next_instruction; // reg == 2
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next_instruction; // reg == 3
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next_instruction; // reg == 4
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next_instruction; // reg == 5
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next_instruction; // reg == 6
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next_instruction; // reg == 7
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// Multiplexed shift single 8-bit
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.at 0xd0;
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width WAUTO, mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_d0_d1;
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.auto_address;
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dispatch_d0_d1:
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem ROLd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RORd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RCLd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RCRd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHLd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHRd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHLd0_d1_reg;
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width WAUTO, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SARd0_d1_reg;
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// Multiplexed shift single 8-bit by immediate
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.at 0xc0;
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width W8, mar_write, mar_wr_sel EA,
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jmp_dispatch_reg dispatch_c0;
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.auto_address;
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dispatch_c0:
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem ROLc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RORc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RCLc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem RCRc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHLc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHRc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SHLc0_reg;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE,
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem SARc0_reg;
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// Multiplexed shift single 16-bit by immediate
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.at 0xc1;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_c1;
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.auto_address;
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dispatch_c1:
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp ROLc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp RORc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp RCLc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp RCRc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp SHLc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp SHRc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp SHLc1;
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width W8, tmp_wr_en, alu_op SELB, b_sel IMMEDIATE, jmp SARc1;
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// Multiplexed shift single 16-bit
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.at 0xd1;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_d0_d1;
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// Multiplexed shift multiple 8-bit
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.at 0xd2;
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width WAUTO, mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_d2_d3;
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.auto_address;
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dispatch_d2_d3:
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp ROLd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp RORd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp RCLd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp RCRd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp SHLd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp SHRd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp SHLd2_d3;
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width WAUTO, ra_modrm_rm_reg, rb_cl, segment DS, jmp SARd2_d3;
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// Multiplexed shift multiple 16-bit
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.at 0xd3;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_d2_d3;
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// Multiplexed neg/mul/not/test/div 8 bit
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.at 0xf6;
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width W8, mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_f6;
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.auto_address;
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dispatch_f6:
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem compANDf6_reg; // reg == 0
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem compANDf6_reg; // reg == 1
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem notf6_reg; // reg == 3
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem negf6_reg; // reg == 3
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem mulf6_reg; // reg == 4
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem imulf6_reg; // reg == 5
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem divf6_reg; // reg == 6
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width W8, ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem idivf6_reg; // reg == 7
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// Multiplexed neg/mul/not/test/div 16 bit
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.at 0xf7;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_f7;
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.auto_address;
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dispatch_f7:
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem compANDf7_reg; // reg == 0
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem compANDf7_reg; // reg == 1
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem notf6_reg; // reg == 2
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem negf6_reg; // reg == 3
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem mulf7_reg; // reg == 4
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem imulf7_reg; // reg == 5
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem divf7_reg; // reg == 6
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem idivf7_reg; // reg == 7
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// Multiplexed push/inc/jmp/call/ff
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.at 0xff;
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mar_write, mar_wr_sel EA, segment DS, jmp_dispatch_reg dispatch_ff;
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.auto_address;
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dispatch_ff:
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem inc_fe_reg; // reg == 0
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem dec_fe_reg; // reg == 1
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem callff_indirect_intra_reg; // reg == 2
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segment_force, segment CS, jmp_rm_reg_mem callff_indirect_inter_reg; // reg == 3
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem jmpff_indirect_intra_reg; // reg == 4
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ra_modrm_rm_reg, segment DS, jmp_rm_reg_mem jmpff_indirect_inter_reg; // reg == 5
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ra_sel SP, segment DS, jmp_rm_reg_mem pushff_reg; // reg == 6
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jmp invalid_opcode;
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.at 0x129;
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jmp reset;
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.auto_address;
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reset:
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel AX;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel CX;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel DX;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel BX;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel BP;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SI;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, rd_sel_source MICROCODE_RD_SEL,
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rd_sel DI;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, segment_force, segment ES,
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segment_wr_en;
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b_sel IMMEDIATE, alu_op SELB, immediate 0xffff, segment_force, segment CS,
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segment_wr_en;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, segment_force, segment SS,
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segment_wr_en;
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b_sel IMMEDIATE, alu_op SELB, immediate 0x0, segment_force, segment DS,
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segment_wr_en;
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next_instruction, jmp opcode_fetch;
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.auto_address;
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write_16_complete:
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segment DS, mem_write, next_instruction;
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write_complete:
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segment DS, mem_write, width WAUTO, next_instruction;
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