mirror of
https://github.com/Gehstock/Mist_FPGA.git
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93 lines
3.5 KiB
Plaintext
93 lines
3.5 KiB
Plaintext
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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.at 0xc3;
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ra_sel SP, jmp retc3;
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.auto_address;
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retc3:
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a_sel RA, alu_op SELA, mar_write, mar_wr_sel Q, segment SS,
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segment_force;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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a_sel MDR, alu_op SELA, load_ip, next_instruction;
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.at 0xc2;
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ra_sel SP, jmp retc2;
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.auto_address;
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retc2:
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a_sel RA, alu_op SELA, mar_write, mar_wr_sel Q, segment SS,
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segment_force;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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a_sel MDR, alu_op SELA, load_ip, ra_sel SP;
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a_sel RA, b_sel IMMEDIATE, alu_op ADD, rd_sel_source
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MICROCODE_RD_SEL, rd_sel SP, next_instruction;
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.at 0xcb;
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ra_sel SP, jmp retcb;
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.auto_address;
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retcb:
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a_sel RA, alu_op SELA, mar_write, mar_wr_sel Q, segment SS,
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segment_force;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, mar_wr_sel Q, mar_write;
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a_sel MDR, alu_op SELA, load_ip, segment_force, segment SS;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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a_sel MDR, alu_op SELA, segment_force, segment CS,
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segment_wr_en, next_instruction;
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.at 0xca;
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ra_sel SP, jmp retca;
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.auto_address;
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retca:
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a_sel RA, alu_op SELA, mar_write, mar_wr_sel Q, segment SS,
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segment_force;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, mar_wr_sel Q, mar_write;
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a_sel MDR, alu_op SELA, load_ip, segment_force, segment SS;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, mar_wr_sel Q, mar_write;
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a_sel MAR, b_sel IMMEDIATE, alu_op ADD, rd_sel_source MICROCODE_RD_SEL,
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rd_sel SP;
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a_sel MDR, alu_op SELA, segment_force, segment CS,
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segment_wr_en, next_instruction;
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// iret
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.at 0xcf;
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ra_sel SP, jmp retcf;
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.auto_address;
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retcf:
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a_sel RA, alu_op SELA, mar_write, mar_wr_sel Q, segment SS,
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segment_force;
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segment SS, segment_force, mem_read, a_sel MAR, b_sel IMMEDIATE,
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immediate 0x2, alu_op ADD, mar_wr_sel Q, mar_write;
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a_sel MDR, alu_op SELA, load_ip, segment_force, segment SS;
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segment SS, segment_force, mem_read;
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a_sel MDR, alu_op SELA, segment_force, segment CS,
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segment_wr_en;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op ADD,
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mar_wr_sel Q, mar_write, segment SS, segment_force;
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segment SS, segment_force, mem_read, a_sel MDR, alu_op SETFLAGSA,
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update_flags CF PF AF ZF SF TF IF DF OF;
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a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op ADD,
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rd_sel SP, rd_sel_source MICROCODE_RD_SEL,
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ext_int_inhibit, next_instruction;
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