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55 lines
1.5 KiB
Verilog
55 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Copyright 2013-2016 Istvan Hegedus
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//
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// FPGATED is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// FPGATED is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Create Date: 09:08:17 12/17/2015
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// Design Name: FPGATED
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// Module Name: mos6529.v
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// Description: MOS 6529 IC emulation.
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//
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// Revision:
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// 0.1 first release
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// 1.0 chip read bug fixed 5/04/2016
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//
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// Additional Comments:
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// CS signal is high active while in real IC it is low active.
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//////////////////////////////////////////////////////////////////////////////////
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module mos6529(
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input clk,
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input [7:0] data_in,
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output wire [7:0] data_out,
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input [7:0] port_in,
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output wire [7:0] port_out,
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input rw,
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input cs
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);
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reg [7:0] iodata=0;
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assign port_out=iodata;
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assign data_out=(cs & rw)?iodata:8'hff;
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always @(posedge clk)
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begin
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if(cs)
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if(rw)
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iodata<=port_in;
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else
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iodata<=data_in;
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end
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endmodule
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