mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-17 16:43:22 +00:00
83 lines
1.7 KiB
VHDL
83 lines
1.7 KiB
VHDL
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
|
|
LIBRARY altera_mf;
|
|
USE altera_mf.all;
|
|
|
|
ENTITY sprom IS
|
|
GENERIC
|
|
(
|
|
init_file : string := "";
|
|
widthad_a : natural;
|
|
width_a : natural := 8;
|
|
outdata_reg_a : string := "UNREGISTERED"
|
|
);
|
|
PORT
|
|
(
|
|
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
|
clock : IN STD_LOGIC ;
|
|
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
|
);
|
|
END sprom;
|
|
|
|
|
|
ARCHITECTURE SYN OF sprom IS
|
|
|
|
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
|
|
|
|
|
|
|
COMPONENT altsyncram
|
|
GENERIC (
|
|
address_aclr_a : STRING;
|
|
clock_enable_input_a : STRING;
|
|
clock_enable_output_a : STRING;
|
|
init_file : STRING;
|
|
intended_device_family : STRING;
|
|
lpm_hint : STRING;
|
|
lpm_type : STRING;
|
|
numwords_a : NATURAL;
|
|
operation_mode : STRING;
|
|
outdata_aclr_a : STRING;
|
|
outdata_reg_a : STRING;
|
|
widthad_a : NATURAL;
|
|
width_a : NATURAL;
|
|
width_byteena_a : NATURAL
|
|
);
|
|
PORT (
|
|
clock0 : IN STD_LOGIC ;
|
|
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
|
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
|
|
BEGIN
|
|
q <= sub_wire0(width_a-1 DOWNTO 0);
|
|
|
|
altsyncram_component : altsyncram
|
|
GENERIC MAP (
|
|
address_aclr_a => "NONE",
|
|
clock_enable_input_a => "BYPASS",
|
|
clock_enable_output_a => "BYPASS",
|
|
init_file => init_file,
|
|
intended_device_family => "Cyclone III",
|
|
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
|
lpm_type => "altsyncram",
|
|
numwords_a => 2**widthad_a,
|
|
operation_mode => "ROM",
|
|
outdata_aclr_a => "NONE",
|
|
outdata_reg_a => outdata_reg_a,
|
|
widthad_a => widthad_a,
|
|
width_a => width_a,
|
|
width_byteena_a => 1
|
|
)
|
|
PORT MAP (
|
|
clock0 => clock,
|
|
address_a => address,
|
|
q_a => sub_wire0
|
|
);
|
|
|
|
|
|
|
|
END SYN;
|