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40 lines
1.0 KiB
Verilog
40 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 19:39:10 05/10/2018
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// Design Name: LS02
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// Module Name: system86/ttl/ls02
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS02 - Quadruple 2-Input Positive-NOR Gates
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS02(
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input wire A1,
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input wire B1,
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input wire A2,
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input wire B2,
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input wire A3,
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input wire B3,
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input wire A4,
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input wire B4,
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output wire Y1,
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output wire Y2,
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output wire Y3,
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output wire Y4
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);
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nor ls02[0:3] ( {Y4, Y3, Y2, Y1}, {A4, A3, A2, A1}, {B4, B3, B2, B1} );
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endmodule
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