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https://github.com/Gehstock/Mist_FPGA.git
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69 lines
1.2 KiB
Verilog
69 lines
1.2 KiB
Verilog
module CHAR_GEN(
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// control
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reset,
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char_code,
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subchar_line,
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subchar_pixel,
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pixel_clock,
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pixel_on
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);
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input pixel_clock;
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input reset;
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input [7:0] char_code;
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input [4:0] subchar_line; // line number within 12 line block
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input [3:0] subchar_pixel; // pixel position within 8 pixel block
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output pixel_on;
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reg [7:0] latched_data;
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reg pixel_on;
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wire [11:0] rom_addr = {char_code[7:0], subchar_line[4:1]};
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wire [7:0] rom_data;
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// instantiate the character generator ROM
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//CHAR_GEN_ROM CHAR_GEN_ROM
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//(
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// pixel_clock,
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// rom_addr,
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// rom_data
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//);
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sprom #(
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.init_file("./roms/charrom_4k.mif"),
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.widthad_a(12),
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.width_a(8))
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CHAR_GEN_ROM(
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.address(rom_addr),
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.clock(pixel_clock),
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.q(rom_data)
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);
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// serialize the CHARACTER MODE data
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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begin
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pixel_on = 1'b0;
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latched_data = 8'h00;
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end
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else begin
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case(subchar_pixel)
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4'b0101:
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latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
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default:
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if(subchar_pixel[0]==1'b0)
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{pixel_on,latched_data [7:1]} <= latched_data [7:0];
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endcase
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end
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end
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endmodule //CHAR_GEN
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