mirror of
https://github.com/Gehstock/Mist_FPGA.git
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94 lines
4.0 KiB
VHDL
94 lines
4.0 KiB
VHDL
--===========================================================================--
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-- --
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-- S Y N T H E S I Z A B L E CRTC6845 C O R E --
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-- --
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-- www.opencores.org - January 2000 --
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-- This IP core adheres to the GNU public license. --
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-- --
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-- VHDL model of MC6845 compatible CRTC --
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-- --
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-- This model doesn't implement interlace mode. Everything else is --
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-- (probably) according to original MC6845 data sheet (except VTOTADJ). --
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-- --
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-- Implementation in Xilinx Virtex XCV50-6 runs at 50 MHz (character clock).--
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-- With external pixel generator this CRTC could handle 450MHz pixel rate --
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-- (see MC6845 datasheet for typical application). --
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-- --
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-- Author: Damjan Lampret, lampret@opencores.org --
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-- --
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-- TO DO: --
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-- --
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-- - fix REG_INIT and remove non standard signals at topl level entity. --
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-- Allow fixed registers values (now set with REG_INIT). Anyway cleanup --
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-- required. --
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-- --
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-- - split design in four units (horizontal sync, vertical sync, bus --
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-- interface and the rest) --
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-- --
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-- - synthesis with Synplify pending (there are some problems with --
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-- UNSIGNED and BIT_LOGIC_VECTOR types in some units !) --
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-- --
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-- - testbench --
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-- --
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-- - interlace mode support, extend VSYNC for V.Total Adjust value (R5) --
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-- --
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-- - verification in a real application --
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-- --
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--===========================================================================--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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entity cursor_ctrl is
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generic (
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RA_WIDTH : natural := 5
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);
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port (
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RESETn : in STD_LOGIC;
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CLK : in STD_LOGIC;
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RA : in STD_LOGIC_VECTOR (RA_WIDTH-1 downto 0);
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CURSOR : out STD_LOGIC;
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ACTIVE : in STD_LOGIC;
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CURST : in STD_LOGIC_VECTOR (6 downto 0);
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CUREND : in STD_LOGIC_VECTOR (4 downto 0)
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);
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end cursor_ctrl;
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architecture cursor_ctrl_behav of cursor_ctrl is
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signal CTR_BLINK : UNSIGNED (4 downto 0);
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begin
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blink_ctr_p:
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process (CLK, RESETn)
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begin
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if RESETn = '0' then
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CTR_BLINK <= (others => '0');
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elsif rising_edge(CLK) then
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CTR_BLINK <= CTR_BLINK + 1;
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end if;
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end process;
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cursor_p:
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process (ACTIVE, CURST, CUREND, RA, CTR_BLINK)
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begin
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if RA >= CURST(4 downto 0) and RA <= CUREND and ACTIVE = '1' then
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case CURST(6 downto 5) is
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when "00" =>
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CURSOR <= '1';
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when "10" =>
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CURSOR <= CTR_BLINK(3);
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when "11" =>
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CURSOR <= CTR_BLINK(4);
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when others =>
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CURSOR <= '0';
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end case;
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else
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CURSOR <= '0';
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end if;
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end process;
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end cursor_ctrl_behav;
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