mirror of
https://github.com/Gehstock/Mist_FPGA.git
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116 lines
2.8 KiB
Verilog
116 lines
2.8 KiB
Verilog
//
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// data_io.v
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//
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// data_io for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module data_io
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(
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input clk_sys,
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input SPI_SCK,
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input SPI_SS2,
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input SPI_DI,
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// ARM -> FPGA download
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output reg ioctl_download = 0, // signal indicating an active download
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output reg [7:0] ioctl_index, // menu index used to upload the file
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output ioctl_wr,
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output reg [24:0] ioctl_addr,
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output reg [7:0] ioctl_dout
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);
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/////////////////////////////// DOWNLOADING ///////////////////////////////
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reg [7:0] data_w;
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reg [24:0] addr_w;
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reg rclk = 0;
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localparam UIO_FILE_TX = 8'h53;
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localparam UIO_FILE_TX_DAT = 8'h54;
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localparam UIO_FILE_INDEX = 8'h55;
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// data_io has its own SPI interface to the io controller
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always@(posedge SPI_SCK, posedge SPI_SS2) begin
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [4:0] cnt;
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reg [24:0] addr;
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if(SPI_SS2) cnt <= 0;
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else begin
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rclk <= 0;
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// don't shift in last bit. It is evaluated directly
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// when writing to ram
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if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
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// increase target address after write
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if(rclk) addr <= addr + 1'd1;
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// count 0-7 8-15 8-15 ...
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if(cnt < 15) cnt <= cnt + 1'd1;
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else cnt <= 8;
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// finished command byte
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if(cnt == 7) cmd <= {sbuf, SPI_DI};
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// prepare/end transmission
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if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
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// prepare
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if(SPI_DI) begin
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addr <= 0;
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ioctl_download <= 1;
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end else begin
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addr_w <= addr;
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ioctl_download <= 0;
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end
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end
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// command 0x54: UIO_FILE_TX
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if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
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addr_w <= addr;
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data_w <= {sbuf, SPI_DI};
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rclk <= 1;
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end
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// expose file (menu) index
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if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
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end
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end
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assign ioctl_wr = |ioctl_wrd;
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reg [1:0] ioctl_wrd;
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always@(negedge clk_sys) begin
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reg rclkD, rclkD2;
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rclkD <= rclk;
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rclkD2 <= rclkD;
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ioctl_wrd<= {ioctl_wrd[0],1'b0};
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if(rclkD & ~rclkD2) begin
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ioctl_dout <= data_w;
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ioctl_addr <= addr_w;
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ioctl_wrd <= 2'b11;
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end
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end
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endmodule
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